Custom Query (93 matches)

Une simulation de la plateforme caba-vgmn-fir-nios2f-new, ./simulation.x 300, après avoir décommenté les traces dans top.cpp, donne le chronogramme des bus VCI target(VciRam) et initiator (VciXcache) (voir fichier attaché).

Dans vci_xcache_wrapper.cpp vous écrivez : VCI formats:

According to the VCI advanced specification, all read command packets (Uncached, Miss data, Miss instruction) are one word packets. For write burst packets, all words must be in the same cache line, and addresses must be contiguous (the BE field is 0 in case of "holes"). The PLEN VCI field is always documented.

D'accord pour la lecture.

Pour l'écriture de paquets (voir chronogramme plen=12) les 3 mots à ecrire sont émis sans attendre RSPVAL. Est ce normal ?

Dans le documentVSI Alliance VCI version 2 april 2001, page 78 il est écrit : "in advanced packet mode ....a write response may have only one cell..". Par contre les chronogrammes figure 38 page 75, figure 34 page 71 (advanced write) ont des RSPVAL qui passe à 1 dès que le premier mot à été écrit, validant ainsi l'écriture des mots suivants.

3. Wagner

• Cannot import SyntheticTask from soclib in vld.task

changing soclib to soclib.hwtask correct bug but should work in the current state (through init.py reexport). May depend on version of Python?

• Add of #include <signal.h> in sc_main.cpp template which was assume to be included from dependencies.

Hi,

I recently updated soclib (I was on revision 1503). With the latest version, it seems that vci_framebuffer is compiled with the SOCLIB_MODULE_DEBUG flag on: it barfs tons of debug on the simulator's terminal.

I double-checked my compilation flags and deleted multiple times my object cache without success. Any idea from where it could come ?