Custom Query (93 matches)

At some point in the simulation, the value of CP0 m_ident becomes completely erratic. In addition, due to the complexity of the code and my lack of experience in C++ debugging, I haven't been able to debug the problem. Important note: the behaviour is exactly the same using either SystemC or SystemCass.

Attached file: the output trace, the simulator files, and the application binary. Here is the command used to launch the simulator:

$ SIMULATION_N_CYCLES=1400000 SIMULATION_N_CPUS=4 ./simulation.x TC

Loader does not contain symbols placed in the BSS section. Although BSS shouldn't be loaded, its symbols should be referenced.

Hello,

I have encoutered some problems with the mips32 iss, I have the following behavior on a miss instruction meanwhile an irq is raised :

t-0 : The mips32 issues an address to the cache wrapper which miss in the tag. The cache wrapper sets the iss_t::InstructionResponse.valid to false (stall the processor).

t-1 : The cache wrapper send a read request to the memory and wait for the response. Meanwhile, the mips32 receive at each cycle a negative response for InstructionResponse.valid.

t-2 : The processor receives an irq, and CHANGES the output adress (next_pc).

t-3 The cache receives the response from the memory and updates the TAG with the NEW address (which is incorrect), because it did not expect that the processor could change the output address beign stalled.

My question is the following : Is a correct behavior for the mips32 to take into account an irq (or other event) meanwhile it is stall ?

I know that on other processors a stall signal freezes the state of the processor, so it will mantain the same output address until it "hits" in the cache.

Thank you for your highlights to this question.