id	summary	reporter	owner	description	type	status	priority	component	resolution	keywords	cc
27	Multi-processor platform with several loaders	alexandre.chagoya-garzon@…	Nicolas Pouillon	"Hi,
I am trying to write a multi-processor platform with private program memories, and I was trying to figure out if this was possible with SOCLIB.
I made a try with 2 Mips in a first phase, with two associated mapping tables. The difference between both mappings is the  MEMORY address, 0x10000000 for Mips0 and 0x20000000 for Mips1. I created two loaders taking different binaries, the reset section of the first jumps to 0x10xxxx and the second jumps to 0x20xxx.

Loader loader0(""MJPEG0.x"");

VciRam<vci_param> vcimultiram0(""vcimultiram0"", IntTab(0,0), maptab, loader0);

Loader loader1(""MJPEG1.x"");

VciRam<vci_param> vcimultiram1(""vcimultiram1"", IntTab(1,0), maptab1, loader1);


MJPEG0.x:

211735 bfc00020:       3c1b1001        lui     k1,0x1001

211736 bfc00024:       277bf360        addiu   k1,k1,-3232

MJPEG1.x:

202290 bfc00020:       3c1b2001        lui     k1,0x2001

202291 bfc00024:       277bb820        addiu   k1,k1,-18400


However, when I execute the simulation, I see that cache1 seems to execute the reset section of MJPEG0.x. 

cache0 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x3c1b1001

cache0 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x277bf360

cache1 PC: 0xbfc00020 NPC: 0xbfc00024 Ins: 0x3c1b1001

cache1 PC: 0xbfc00024 NPC: 0xbfc00028 Ins: 0x277bf360

Did I do something wrong?

Thank you
Alexandre"	helpdesk	closed	N/A	IP-Cores	fixed	multi-processor, separated program memory space