| | 1 | [wiki:Component SocLib Components General Index] |
| | 2 | |
| | 3 | '''UNDER DEVELOPMENT''' |
| | 4 | |
| | 5 | = ARM7TDMI Processor Functional Description = |
| | 6 | |
| | 7 | This hardware component is a ARM7TDMI processor core. This is only an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper]. |
| | 8 | |
| | 9 | The simulation model is actually an instruction set simulator with an ARM7TDMI pipeline. |
| | 10 | |
| | 11 | Currently it only exists in bigendian form. |
| | 12 | |
| | 13 | = Component definition = |
| | 14 | |
| | 15 | Available in source:trunk/soclib/soclib/lib/arm7tdmi/metadata/arm7tdmi.sd |
| | 16 | |
| | 17 | == Usage == |
| | 18 | |
| | 19 | ARM7TDMI has no parameters. |
| | 20 | {{{ |
| | 21 | Uses('iss_wrapper', iss_t = 'common:arm7tdmi') |
| | 22 | }}} |
| | 23 | |
| | 24 | Before compiling any SoClib simulator using the ARM7TDMI you will need to download the UNISIM ([http:\\www.unisim.org]) library. |
| | 25 | To do so just download it using svn from [https://unisim.org/svn/devel/unisim_lib] with the following command: |
| | 26 | svn import https://unisim.org/svn/devel/unisim_lib |
| | 27 | You will have to enter a username and password. If you do not have access to the UNISIM development, you can simply use 'guest'/'guest' for username and password respectively. |
| | 28 | |
| | 29 | = ARM7TDMI Processor ISS Implementation = |
| | 30 | |
| | 31 | The implementation is in |
| | 32 | * source:trunk/soclib/lib/arm7tdmi/include/iss/arm7tdmi.h |
| | 33 | * source:trunk/soclib/lib/arm7tdmi/src/iss/arm7tdmi.cpp |
| | 34 | |
| | 35 | The previous files use the ARM7TDMI implementation provided in the UNISIM library. |
| | 36 | |
| | 37 | |
| | 38 | == Template parameters == |
| | 39 | |
| | 40 | This component has no template parameters. |
| | 41 | |
| | 42 | == Constructor parameters == |
| | 43 | |
| | 44 | {{{ |
| | 45 | MipsElIss( |
| | 46 | sc_module_name name, // Instance Name |
| | 47 | int ident); // processor id |
| | 48 | }}} |
| | 49 | or |
| | 50 | {{{ |
| | 51 | MipsEbIss( name, ident); |
| | 52 | }}} |
| | 53 | |
| | 54 | == Visible registers == |
| | 55 | |
| | 56 | The following internal registers define the processor internal state, and can be inspected: |
| | 57 | * r_pc : Program counter |
| | 58 | * m_ins : Instruction register |
| | 59 | * r_gpr[i] : General registers ( 0 < i < 32) |
| | 60 | * r_hi & r_lo : Intermediate registers for multiply / divide instructions |
| | 61 | * r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values: |
| | 62 | * 8: BAR : Bad address register |
| | 63 | * 12: SR : Status register |
| | 64 | * 13: CR : Cause register |
| | 65 | * 14: EPC : Exception PC register |
| | 66 | * 15: INFOS : CPU identification number on bits ![9:0] |
| | 67 | |
| | 68 | == Interrupts == |
| | 69 | |
| | 70 | Mips defines 6 interrupts lines. ~~Le lowest number has the hiest priority.~~ |
| | 71 | The handling and prioritization of the interrupts is deferred to software. |
| | 72 | |
| | 73 | == Ports == |
| | 74 | |
| | 75 | None, it is to the wrapper to provide them. |
