Changes between Version 3 and Version 4 of Component/ARM7TDMI
- Timestamp:
- Jun 13, 2008, 12:55:26 PM (16 years ago)
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Component/ARM7TDMI
v3 v4 47 47 48 48 {{{ 49 MipsElIss(49 ARM7TDMIIss( 50 50 sc_module_name name, // Instance Name 51 51 int ident); // processor id 52 }}}53 or54 {{{55 MipsEbIss( name, ident);56 52 }}} 57 53 58 54 == Visible registers == 59 55 60 The following internal registers define the processor internal state, and can be inspected: 61 * r_pc : Program counter 62 * m_ins : Instruction register 63 * r_gpr[i] : General registers ( 0 < i < 32) 64 * r_hi & r_lo : Intermediate registers for multiply / divide instructions 65 * r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values: 66 * 8: BAR : Bad address register 67 * 12: SR : Status register 68 * 13: CR : Cause register 69 * 14: EPC : Exception PC register 70 * 15: INFOS : CPU identification number on bits ![9:0] 56 '''UNDER DEVELOPMENT''' 71 57 72 58 == Interrupts == 73 59 74 Mips defines 6 interrupts lines. ~~Le lowest number has the hiest priority.~~ 60 '''UNDER DEVELOPMENT''' 75 61 The handling and prioritization of the interrupts is deferred to software. 76 62
