Changes between Version 3 and Version 4 of Component/ARM7TDMI


Ignore:
Timestamp:
Jun 13, 2008, 12:55:26 PM (17 years ago)
Author:
gracia
Comment:

--

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  • Component/ARM7TDMI

    v3 v4  
    4747
    4848{{{
    49 MipsElIss(
     49ARM7TDMIIss(
    5050     sc_module_name name,   //  Instance Name
    5151     int  ident);   // processor id
    52 }}}
    53 or
    54 {{{
    55 MipsEbIss( name, ident);
    5652}}}
    5753
    5854== Visible registers ==
    5955
    60  The following internal registers define the processor internal state, and can be inspected:
    61  * r_pc : Program counter
    62  * m_ins : Instruction register
    63  * r_gpr[i] : General registers ( 0 < i < 32)
    64  * r_hi & r_lo : Intermediate registers for multiply / divide instructions
    65  * r_cp0[i] : Coprocessor 0 registers (0<=i<32). Implemented values:
    66   *  8: BAR : Bad address register
    67   * 12: SR : Status register
    68   * 13: CR : Cause register
    69   * 14: EPC : Exception PC register
    70   * 15: INFOS : CPU identification number on bits ![9:0]
     56'''UNDER DEVELOPMENT'''
    7157
    7258== Interrupts ==
    7359
    74 Mips defines 6 interrupts lines. ~~Le lowest number has the hiest priority.~~
     60'''UNDER DEVELOPMENT'''
    7561The handling and prioritization of the interrupts is deferred to software.
    7662