| 1 | |
| 2 | [[PageOutline]] |
| 3 | |
| 4 | = Simulation API = |
| 5 | |
| 6 | This new API is an evolution of [wiki:Component/IssApi the ISS API]. |
| 7 | New features are: |
| 8 | * Use structs rather than arguments, this eases API evolution (which can be acomplished through carefully choosed default values); |
| 9 | * support for CPU modes; |
| 10 | * support for generic Memory management unit. |
| 11 | |
| 12 | == Structures and values == |
| 13 | |
| 14 | === Enumerated values === |
| 15 | |
| 16 | Execution mode for any Instruction/Data access, checked by |
| 17 | mode-enabled caches |
| 18 | {{{ |
| 19 | enum ExecMode { |
| 20 | MODE_HYPER, |
| 21 | MODE_KERNEL, |
| 22 | MODE_USER, |
| 23 | }; |
| 24 | }}} |
| 25 | |
| 26 | Operation type on Data cache access |
| 27 | {{{ |
| 28 | enum DataOperationType { |
| 29 | DATA_READ, |
| 30 | DATA_WRITE, |
| 31 | DATA_LL, |
| 32 | DATA_SC, |
| 33 | XTN_WRITE, |
| 34 | XTN_READ, |
| 35 | }; |
| 36 | }}} |
| 37 | |
| 38 | When operation is XTN_READ or XTN_WRITE, address field must be |
| 39 | one of these values, it determines the extended access type. |
| 40 | {{{ |
| 41 | enum ExternalAccessType { |
| 42 | XTN_PTPR, |
| 43 | XTN_TLB_EN, |
| 44 | XTN_ICACHE_FLUSH, |
| 45 | XTN_DCACHE_FLUSH, |
| 46 | XTN_ITLB_INVAL, |
| 47 | XTN_DTLB_INVAL, |
| 48 | XTN_ICACHE_INVAL, |
| 49 | XTN_DCACHE_INVAL, |
| 50 | XTN_ICACHE_PREFETCH, |
| 51 | XTN_DCACHE_PREFETCH, |
| 52 | XTN_SYNC, |
| 53 | XTN_INS_ERROR_TYPE, |
| 54 | XTN_DATA_ERROR_TYPE, |
| 55 | XTN_INS_BAD_VADDR, |
| 56 | XTN_DATA_BAD_VADDR, |
| 57 | }; |
| 58 | }}} |
| 59 | |
| 60 | === Instruction request and response === |
| 61 | |
| 62 | Instruction request, only significant if `valid' is asserted. |
| 63 | addr must be 4-byte aligned. |
| 64 | {{{ |
| 65 | struct InstructionRequest { |
| 66 | bool valid; |
| 67 | addr_t addr; |
| 68 | enum ExecMode mode; |
| 69 | }; |
| 70 | }}} |
| 71 | |
| 72 | |
| 73 | Instruction response. |
| 74 | |
| 75 | Valid is asserted when query has beed satisfied, if no request |
| 76 | is pending, valid is not asserted. |
| 77 | |
| 78 | instruction is only valid if no error is signaled. |
| 79 | {{{ |
| 80 | struct InstructionResponse { |
| 81 | bool valid; |
| 82 | bool error; |
| 83 | data_t instruction; |
| 84 | }; |
| 85 | }}} |
| 86 | |
| 87 | === Data request and response === |
| 88 | |
| 89 | Data request, only significant if `valid' is asserted. |
| 90 | addr must be 4-byte aligned. |
| 91 | wdata is only significant for be-masked bytes. |
| 92 | * wdata![7:0] is at ![addr], masked by be![0] |
| 93 | * wdata![15:8] is at ![addr+1], masked by be![1] |
| 94 | * wdata![23:16] is at ![addr+2], masked by be![2] |
| 95 | * wdata![31:24] is at ![addr+3], masked by be![3] |
| 96 | |
| 97 | When type is XTN_READ or XTN_WRITE, addr must be an opcod of |
| 98 | enum !ExternalAccessType. For extended access types needing an |
| 99 | address, address is passed through the wdata field. |
| 100 | {{{ |
| 101 | struct DataRequest { |
| 102 | bool valid; |
| 103 | addr_t addr; |
| 104 | data_t wdata; |
| 105 | enum DataOperationType type; |
| 106 | be_t be; |
| 107 | enum ExecMode mode; |
| 108 | }; |
| 109 | }}} |
| 110 | |
| 111 | |
| 112 | Data response. |
| 113 | |
| 114 | Valid is asserted when query has beed satisfied, if no request |
| 115 | is pending, valid is not asserted. |
| 116 | |
| 117 | data is only valid if no error is signaled. |
| 118 | |
| 119 | Read data is aligned with the same semantics than the wdata |
| 120 | field in struct !DataRequest. Only bytes asserted in the BE |
| 121 | field upon request are meaningful, others have an undefined |
| 122 | value, they may be non-zero. |
| 123 | {{{ |
| 124 | struct DataResponse { |
| 125 | bool valid; |
| 126 | bool error; |
| 127 | data_t rdata; |
| 128 | }; |
| 129 | }}} |
| 130 | |
| 131 | == Functions == |
| 132 | |
| 133 | === void reset() === |
| 134 | |
| 135 | Reset operation, Iss must behave like the processor receiving a reset cycle. |
| 136 | |
| 137 | Tell the Iss to execute *at most* ncycle cycles, knowing the |
| 138 | value of all the irq lines. Each irq is a bit in the |
| 139 | irq_bit_field word. |
| 140 | |
| 141 | === uint32_t executeNCycles( uint32_t ncycle, uint32_t irq_bit_field ) === |
| 142 | |
| 143 | Iss must return the number of cycles it actually executed. This |
| 144 | is at least 1, at most ncycle. |
| 145 | |
| 146 | === void getInstructionRequest( struct !InstructionRequest & ) === |
| 147 | |
| 148 | Iss must populate the request fields. |
| 149 | |
| 150 | === void setInstruction( const struct !InstructionResponse & ) === |
| 151 | |
| 152 | Iss is given back the response. It may not be valid. |
| 153 | |
| 154 | === void getDataRequest( struct !DataRequest & ) === |
| 155 | |
| 156 | Iss must populate the request fields. |
| 157 | |
| 158 | === void setData( const struct !DataResponse & ) === |
| 159 | |
| 160 | Iss is given back the response. It may not be valid. |
| 161 | |
| 162 | === void setWriteBerr() === |
| 163 | |
| 164 | The cache received an imprecise write error condition, this |
| 165 | signalling is asynchronous. |
| 166 | |
| 167 | = Other APIs = |
| 168 | |
| 169 | == Sideband signals == |
| 170 | |
| 171 | In order to inform the ISS about some cache caracteristics, those functions have been defined. |
| 172 | |
| 173 | Their implementation is optional. |
| 174 | |
| 175 | === void setICacheInfo( size_t line_size, size_t assoc, size_t n_lines ) === |
| 176 | |
| 177 | Inform the Iss about the instruction cache caracteristics |
| 178 | |
| 179 | === void setDCacheInfo( size_t line_size, size_t assoc, size_t n_lines ) === |
| 180 | |
| 181 | Inform the Iss about the data cache caracteristics |
| 182 | |
| 183 | == Debugger API == |
| 184 | |
| 185 | This API is optional, it serves to expose the internal ISS registers to a debugger. |
| 186 | |
| 187 | The debugger API is ISS-architecture independant. |
| 188 | |
| 189 | === unsigned int debugGetRegisterCount() === |
| 190 | |
| 191 | Iss must return the count of registers known to GDB. This must |
| 192 | follow GDB protocol for this architecture. |
| 193 | |
| 194 | === debug_register_t debugGetRegisterValue(unsigned int reg) === |
| 195 | |
| 196 | Accessor for an Iss register, register number meaning is |
| 197 | defined in GDB protocol for this architecture. |
| 198 | |
| 199 | === void debugSetRegisterValue(unsigned int reg, debug_register_t value) === |
| 200 | |
| 201 | Accessor for an Iss register, register number meaning is |
| 202 | defined in GDB protocol for this architecture. |
| 203 | |
| 204 | === size_t debugGetRegisterSize(unsigned int reg) === |
| 205 | |
| 206 | Get the size for a given register. This is defined in GDB |
| 207 | protocol for this architecture. |
| 208 | |
| 209 | === addr_t debugGetPC() === |
| 210 | |
| 211 | Get the current PC |
| 212 | |
| 213 | === void debugSetPC(addr_t) === |
| 214 | |
| 215 | Set the current PC |