Changes between Version 11 and Version 12 of Component/Iss2Api
- Timestamp:
- Feb 12, 2013, 12:54:09 PM (12 years ago)
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Component/Iss2Api
v11 v12 37 37 38 38 When operation is XTN_READ or XTN_WRITE, address field must be 39 one of these values, it determines the extended access type.39 one of these values, that determines the extended access type. 40 40 41 41 || register name || index || description || mode || … … 47 47 || MMU_ITLB_INVAL || 4 || Instruction TLB line invalidation || W || 48 48 || MMU_DTLB_INVAL || 5 || Data TLB line Invalidation || W || 49 || MMU_ICACHE_INVAL || 6 || Inst ruction Cache line invalidation|| W ||50 || MMU_DCACHE_INVAL || 7 || Data Cache line invalidation 49 || MMU_ICACHE_INVAL || 6 || Inst Cache line invalidation (vaddr) || W || 50 || MMU_DCACHE_INVAL || 7 || Data Cache line invalidation (vaddr) || W || 51 51 || MMU_ICACHE_PREFETCH || 8 || Instruction Cache line prefetch || W || 52 52 || MMU_DCACHE_PREFETCH || 9 || Data Cache line prefetch || W || … … 58 58 || MMU_PARAMS || 15 || Caches & TLBs hardware parameters || R || 59 59 || MMU_RELEASE || 16 || Generic MMU release number || R || 60 || MMU_WORD_LO || 17 || LSB for double word access || R/W || 61 || MMU_WORD_HI || 18 || MSB for double word access || R/W || 62 || MMU_ICACHE_PA_INVAL || 19 || Inst Cache line invalidation (paddr) || W || 63 || MMU_DCACHE_PA_INVAL || 20 || Data Cache line invalidation (paddr) || W || 64 || MMU_LL_RESET || 21 || LLSC reservation buffer invalidation || W || 60 65 61 66 === Instruction request ===
