Changes between Version 5 and Version 6 of Component/Iss2Api

Timestamp:

Oct 22, 2009, 11:12:05 AM (15 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Iss2Api

@@ -38 +38 @@
 When operation is XTN_READ or XTN_WRITE, address field must be
 one of these values, it determines the extended access type.
-{{{
-    enum ExternalAccessType {
-        XTN_PTPR,
-        XTN_TLB_EN,
-        XTN_ICACHE_FLUSH,
-        XTN_DCACHE_FLUSH,
-        XTN_ITLB_INVAL,
-        XTN_DTLB_INVAL,
-        XTN_ICACHE_INVAL,
-        XTN_DCACHE_INVAL,
-        XTN_ICACHE_PREFETCH,
-        XTN_DCACHE_PREFETCH,
-        XTN_SYNC,
-        XTN_INS_ERROR_TYPE,
-        XTN_DATA_ERROR_TYPE,
-        XTN_INS_BAD_VADDR,
-        XTN_DATA_BAD_VADDR,
-    };
-}}}
+
+|| register name         || index || description                               || mode ||
+||                       ||       ||                                           ||      ||
+|| MMU_PTPR              ||   0   || Page Table Pointer Register               || R/W  ||
+|| MMU_MODE              ||   1   || Data & Inst TLBs and caches Mode Register || R/W  ||
+|| MMU_ICACHE_FLUSH      ||   2   || Instruction Cache flush                   || W    ||
+|| MMU_DCACHE_FLUSH      ||   3   || Data Cache flush                          || W    ||
+|| MMU_ITLB_INVAL        ||   4   || Instruction TLB line invalidation         || W    ||
+|| MMU_DTLB_INVAL        ||   5   || Data TLB line Invalidation                || W    ||
+|| MMU_ICACHE_INVAL      ||   6   || Instruction Cache line invalidation       || W    ||
+|| MMU_DCACHE_INVAL      ||   7   || Data Cache line invalidation              || W    ||
+|| MMU_ICACHE_PREFETCH   ||   8   || Instruction Cache line prefetch           || W    ||
+|| MMU_DCACHE_PREFETCH   ||   9   || Data Cache line prefetch                  || W    ||
+|| MMU_SYNC              ||  10   || Complete pending writes                   || W    ||
+|| MMU_IETR              ||  11   || Instruction Exception Type Register       || R    ||
+|| MMU_DETR              ||  12   || Data Exception Type Register              || R    ||
+|| MMU_IBVAR             ||  13   || Instruction Bad Virtual Address Register  || R    ||
+|| MMU_DBVAR             ||  14   || Data Bad Virtual Address Register         || R    || 
+|| MMU_PARAMS            ||  15   || Caches & TLBs hardware parameters         || R    || 
+|| MMU_RELEASE           ||  16   || Generic MMU release number                || R    ||
 
 === Instruction request and response ===