| 1 | |
| 2 | [[PageOutline]] |
| 3 | |
| 4 | Function '''step()''' is the main entry point, it executes one ISS step : |
| 5 | * For an untimed model (PV wrapper) one step corresponds to one instruction. |
| 6 | * For a timed model (CABA wrapper or TLM-T wrapper), one step corresponds to one cycle. |
| 7 | |
| 8 | |
| 9 | = API = |
| 10 | |
| 11 | == inline void reset() == |
| 12 | |
| 13 | This function resets all registers defining the processor internal state. |
| 14 | |
| 15 | == inline bool isBusy() == |
| 16 | |
| 17 | This function is only used by timed wrappers (CABA & TLM-T). In RISC processors, most instructions have a visible latency of one cycle. But some instructions (such as multiplication or division) can have a visible latency longer than one cycle. This function is called by the CABA and TLM-T wrappers before executing one step : If the processor is busy, the wrapper calls the '''nullStep()''' function. If the processor is available, the wrapper may call the '''step()''' function to execute one instruction. |
| 18 | |
| 19 | == inline void step() == |
| 20 | |
| 21 | This function executes one instruction. All processor internal registers can be modified. |
| 22 | |
| 23 | == inline void nullStep( int ncycles = 1 ) == |
| 24 | |
| 25 | This function performs one internal step of a long instruction. |
| 26 | |
| 27 | * `ncycles`: number of cycles to pass with nothing to do, defaults to 1 |
| 28 | |
| 29 | == inline void getInstructionRequest (bool & req , uint32_t & address) == |
| 30 | |
| 31 | This function is used by the wrappers to obtain from the ISS the instruction request parameters. |
| 32 | |
| 33 | * `req`: whether there is a request |
| 34 | * `address`: address of instruction to fetch, must be 4-byte aligned |
| 35 | |
| 36 | == inline void getDataRequest (bool &req , enum !DataAccessType & type, uint32_t & address, uint32_t & wdata) == |
| 37 | |
| 38 | This function is used by the wrapper to obtain from the ISS the data request parameters. |
| 39 | |
| 40 | * `req`: whether there is a request |
| 41 | * `type`: access type, see below |
| 42 | * `address`: address of data access |
| 43 | * `wdata`: data to store, only meaningful for write access types |
| 44 | |
| 45 | Type is one of: |
| 46 | {{{ |
| 47 | enum DataAccessType { |
| 48 | READ_WORD, // Read Word |
| 49 | READ_HALF, // Read Half |
| 50 | READ_BYTE, // Read Byte |
| 51 | LINE_INVAL, // Cache Line Invalidate |
| 52 | WRITE_WORD, // Write Word |
| 53 | WRITE_HALF, // Write Half |
| 54 | WRITE_BYTE, // Write Byte |
| 55 | STORE_COND, // Store Conditional Word |
| 56 | READ_LINKED, // Load Linked Word |
| 57 | } |
| 58 | }}} |
| 59 | |
| 60 | == inline void setInstruction (bool error, uint32_t ins) == |
| 61 | |
| 62 | This function is used by the wrapper to transmit to the ISS. |
| 63 | |
| 64 | * `error`: whether there was an error |
| 65 | * `ins`: instruction for asked address |
| 66 | |
| 67 | == inline void setDataResponse (bool error, uint32_t rdata) == |
| 68 | |
| 69 | This function is used by the wrapper to transmit to the ISS, the response to the data request. |
| 70 | |
| 71 | * `error`: whether there was an error |
| 72 | * `rdata`: data for asked memory region, only meaningful if access is a read |
| 73 | |
| 74 | In any case, this function must reset the ISS data request. |
| 75 | |
| 76 | == inline void setWriteBerr () == |
| 77 | |
| 78 | This function is used by the wrapper to signal asynchronous bus errors, in case of a write acces, that is non blocking for the processor. |
| 79 | |
| 80 | == inline void setIrq (uint32_t irq) == |
| 81 | |
| 82 | This function is used by the wrapper to signal the current values of the interrupt lines (as a bitfield) on each cycle. |
| 83 | |
| 84 | For each processor, the number of hardware interrupt lines must be defined by the ISS static variable '''n_irq''', and is limited to 32. |