Version 1 (modified by andriami@…, 14 years ago) (diff)


SocLib Components General Index


1) Functional Description

This component is a generic mailbox: it can contain up to 256 independent, software mailbox. This mailbox allows several processors to communicate via an interrupt mechanism.

There are two sets of registers per mailbox: one to send messages from a processor P1 to a processor P2 and one to issue an interrupt to a processor P2. Each set of mailbox registers consists of three 16-bit registers and a 1-bit flag register. The interrupting processor can use two 16-bit registers to pass data words to the interrupted processor and the other 16-bit register to pass a command word. Writing a command word in the mailbox generates an interrupt signal to the component which address has been specified. The mailboxes are located in the shared memory space. Each mailbox takes 12 bytes in the address space, and is seen as 3 memory mapped registers:

  • COMMAND[i] @ BASE + 0
    A write request sets a command in the COMMAND[i] register and generates an interrupt on the corresponding index. A read request returns the value on the COMMAND[i] register.
  • DATA_W[i] @ BASE + 4
    A write request set the data in the DATA_W[i] register.
    A read request returns the value of the DATA_W[i] register.
  • none @ BASE + 8
    Free space for others data...
  • RESET_ADR[i] @ BASE + 12
    Any write request resets the RESET_ADR[i] register to false.
    A read request returns the 0 value if RESET_ADR[i] is false.

2) Component definition & usage

Component definition


Mailbox has a Nirq parameter, which defines the number of processors that can be interrupted through the mailbox number. For example with two processors:

Uses('mailbox', Nirq = 2);

3) CABA Implementation

CABA sources

CABA Constructor parameters

          sc_module_name	insname, 		// instance name
	  const soclib::common::IntTab 	&index,		// VCI target index
	  const soclib::common::MappingTable 	&mt     // segment table

CABA Ports

  • sc_in<bool> p_resetn : hardware reset
  • sc_in<bool> p_clk : clock
  • soclib::caba::VciTarget<vci_param> p_vci : The VCI port
  • sc_out<bool> p_irq [Nirq] : Interrupts ports array

4) TLM-T Implementation

The TLM-T implementation is not yet available.