Changes between Version 10 and Version 11 of Component/Mapping Table

Timestamp:

Feb 11, 2008, 11:30:44 AM (16 years ago)

Author:

alain

Comment:

--

Component/Mapping Table

@@ -66 +66 @@
 This segment is associated to target no 2 in cluster no 3. It is cacheable.
 
-=== Cacheability ===
+== 3) Cacheability Table ==
 
 Cacheability is a by-segment attribute. Cacheability is implemented by the [wiki:Component/VciXcache VciXcache] component. As this component does not implement a MMU, it contains a dedicated address decoder to determine the cacheability. This decoder is implemented as a '''Cacheability Table'''. 
-This table is indexed by the address bits defined by the cacheability_mask, and contains the
-Boolean defining the cacheability.
+This table is accessed by the cache controller for each processor request. This table is indexed by the 
+address bits defined by the cacheability_mask, and contains the Boolean defining the cacheability.
 
 The content of the '''Cacheability Table''' is automatically constructed by a method of the mapping table.
 Of course, the mapping of the cacheable segments must be consistent with the cacheability mask defined in the mapping table.  This is checked by the mapping table, and you'll get an `"Incoherent MappingTable" exception` if the mapping is inconsistent.
 
-== 3) examples ==
+== 4) Routing Tables ==
 
 === One level interconnect ===