Changes between Version 12 and Version 13 of Component/Mapping Table


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Timestamp:
Feb 11, 2008, 11:39:57 AM (17 years ago)
Author:
alain
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  • Component/Mapping Table

    v12 v13  
    1414and the mapping of the segments on the VCI physical targets.
    1515
    16 From this centralized description, it is possible to derive the '''routing tables''' used by the
     16From this centralized description, it is possible to derive the '''Routing Tables''' used by the
    1717hardware interconnect components to decode the VCI address, and route the VCI packets to
    1818the proper VCI target. It is also possible to derive the '''Cacheability Table''' used by the
    … …  
    4949 * a name
    5050 * a base address
    51  * a size
     51 * a size (number of bytes)
    5252 * a target_index (an !IntTab)
    5353 * a cacheability flag
    5454
    55 The size field is a number of bytes. The target_index field identifies the VCI target that contains
     55The target_index field identifies the VCI target that contains
    5656the corresponding segment, and is used by the interconnect to route a command packet to the proper target.
    5757The cacheability field is used by the [wiki:Component/VciXcache VciXcache] component to define if the corresponding segment is cacheable. All segments defined by the system designer for a given architecture must be non-overlaping.
    … …  
    6262}}}
    6363
    64 This segment is associated to target no 2 in cluster no 3. It is cacheable.
     64In this example, the segment is associated to target no 2 in cluster no 3, and is cacheable.
    6565
    66 == 3) Cacheability Table ==
    67 
    68 Cacheability is a by-segment attribute. Cacheability is implemented by the [wiki:Component/VciXcache VciXcache] component. As this component does not implement a MMU, it contains a dedicated address decoder to determine the cacheability. This decoder is implemented as a '''Cacheability Table'''.
    69 This table is accessed by the cache controller for each processor request. This table is indexed by the
    70 address bits defined by the cacheability_mask, and contains the Boolean defining the cacheability.
    71 
    72 The content of the '''Cacheability Table''' is automatically constructed by a method of the mapping table.
    73 Of course, the mapping of the cacheable segments must be consistent with the cacheability mask defined in the mapping table.  This is checked by the mapping table, and you'll get an `"Incoherent MappingTable" exception` if the mapping is inconsistent.
    74 
    75 == 4) Routing Tables ==
     66== 3) Routing Tables ==
    7667
    7768=== One level interconnect ===
    … …  
    117108 * It generates - for each cluster - the '''Local Routing Table''', implemented as a ROM by the local interconnect. This table is indexed by the VCI ADDRESS LSB bits and contains the target local index. Depending on the mapping, each cluster can have a different Local Routing Table.
    118109
     110== 4) Cacheability Table ==
     111
     112Cacheability is a by-segment attribute. Cacheability is implemented by the [wiki:Component/VciXcache VciXcache] component. As this component does not implement a MMU, it contains a dedicated address decoder to determine the cacheability. This decoder is implemented as a '''Cacheability Table'''.
     113This table is accessed by the cache controller for each processor request. This table is indexed by the
     114address bits defined by the cacheability_mask, and contains the Boolean defining the cacheability.
     115
     116The content of the '''Cacheability Table''' is automatically constructed by a method of the mapping table.
     117Of course, the mapping of the cacheable segments must be consistent with the cacheability mask defined in the mapping table.  This is checked by the mapping table, and you'll get an `"Incoherent MappingTable" exception` if the mapping is inconsistent.