Changes between Version 1 and Version 2 of Component/Mapping Table

Timestamp:

May 16, 2007, 6:36:10 PM (17 years ago)

Author:

alain

Comment:

--

Component/Mapping Table

@@ -7 +7 @@
 the SoCLib hardware components.
 
-All VCI initiatores and VCI targets share the same "flat" address space, but the address decoding 
-scheme supports a multi-level structured interconnect.
+This object is basically an associative table, where each entry define a segment descriptor.
+A segment is a set of consecutive addresses in the address space. Each segment has a name, and is characterized by the following fields:
+ * string '''name'''
+ * addr_t '''base_address''' 
+ * size_t '''size'''
+ * IntTab '''target_index'''
+ * bool '''cacheability'''
+The size field is a number of bytes. The target_index field identifies the VCI target that contains
+the corresponding segment, and is used by the interconnect to route a command packet to the proper target.
+The cacheability field can be used by the cache controllers to define if the corresponding segment is cacheable.
+
+All segments defined by the system designer for a given architecture must be non-overlaping.
+
+Therefore, the mapping table is a centralized description of both the address space segmentation,
+the mapping of the segments on the hardware architecture physical targets.
+From this centralized description, it is possible to derive the '''routing tables''' used by the 
+hardware interconnect to route the VCI packets to the proper target, depending of the VCI address.
+
+All VCI initiators and VCI targets share the same  address space, but the address decoding 
+scheme can support a structured interconnect.
 
 == One level interconnect ==
 
-This is the simplest case:
+This is the simplest case, where all VCI targets and VCI initiators are connected to a "flat" interconnect.
  * each VCI component is identified by a simple index.
- * and all VCI targets must have different indexes. Most hardware interconnects (such as the make the assumption that the target indexes 
- * each VCI  is identified by a simple index, and all initiators must have different indexes. The initiator index
-must be equal to the VCI SRCID value.
- * The VCI address is structured in two fields
- 
+ * all VCI targets must have different indexes. 
+ * all VCI initiators must have different indexes. 
+ * The initiator index must be equal to the VCI SRCID value. Most hardware interconnects (such as the PibusBcu or the VciVgmn components) make the assumption that the initiator indexes are between 0 and M -1 , where M is the total number of VCI initiators. 
+ * The VCI ADDRESS field is structured in two fields:  | MSB | OFFSET |
+   * The MSB field is decoded by the flat interconnect to route the command packet to the proper VCI target.
+   * The OFFSET field is decoded by the VCI target.
+ * The VCI SRCID field is used by the interconnect to route the response packet to the proper VCI initiator.
+ * Most flat hardware interconnects (such as the PibusBcu or the VciVgmn components) make the assumption that the target indexes are between 0 and T -1 (where T is the total number of VCI targets), and the initiator indexes are between 0 and M -1 (where M is the total number of VCI initiators). 
+
+Therefore, the flat interconnect must contain a ROM implementing a '''routing table''' indexed by the
+VCI ADDRESS MSB bits and containing the corresponding target index.
+The content of this '''routing table''' is automatically computed by a method associated to the mapping table.
+
 == Two level interconnect ==
 
-The hardware architecture is supposed to be split into several subsystems (or clusters),
-with a global interconnect for inter-cluster communications, and one local interconnect in
+With a two level interconnect, the hardware architecture is supposed to be split into several subsystems 
+(or clusters), with a global interconnect for inter-cluster communications, and one local interconnect in
 each cluster for intra-cluster communications.
 
  * each VCI component is identified by a structured index containing two indexes:
-   * a global index that is the subsystem (or cluster) index.
+   * a global index that identifies the subsystem (or cluster) index.
    * a local index, that identifies the VCI component in the cluster.
- * All , and all targets must have different indexes. Most hardware interconnects (such as the make the assumption that the target indexes 
- * each VCI  is identified by a simple index, and all initiators must have different indexes. The initiator index
-must be equal to the VCI SRCID value.
+ * all VCI targets in the same cluster must have the same global index.
+ * all VCI targets in the same cluster must have different local indexes.
+ * all VCI initiators in the same cluster must have the same global index.
+ * all VCI initiators in the same cluster must have different local indexes.
+ * The VCI ADDRESS field is structured in three fields : | MSB | LSB | OFFSET |
+   * The MSB field is decoded by the global interconnect to route the command packet to the proper cluster. 
+   * The LSB field is decoded by the local interconnect to route the command packet to the proper target.
+   * The OFFSET field is decoded by the VCI target.
+ * The VCI SRCID field is structured in two fields : | MSB | LSB |
+   * The SRCID MSB field must be equal to the initiator global index.
+   * The SRCID LSB field must be equal to the initiator local index.
 
-
-eand each VCI component is identified
-by abut the address decoding
-scheme supports. 
+The services provided by the Mapping Table for a two level interconnect are the following :
+ * It generates the '''Global Routing Table''', indexed by the VCI ADDRESS MSB bits, and containing the corresponding global index (cluster index). This Global Routing Table is used by the global interconnect.
+ * It generates - for each cluster - the '''Local Routing Table''', indexed by the VCI ADDRESS LSB bits and containing the corresponding target local index. Depending on the mapping, each cluster can have a different Local Routing Table.