Changes between Version 4 and Version 5 of Component/Mapping Table


Ignore:
Timestamp:
May 17, 2007, 10:55:37 AM (18 years ago)
Author:
Nicolas Pouillon
Comment:

Component links

Legend:

Unmodified
Added
Removed
Modified

  • Component/Mapping Table

    v4 v5  
    3434 * all VCI targets must have different indexes.
    3535 * all VCI initiators must have different indexes.
    36  * The initiator index must be equal to the VCI SRCID value. Most hardware interconnects (such as the PibusBcu or the VciVgmn components) make the assumption that the initiator indexes are between 0 and M -1 , where M is the total number of VCI initiators.
     36 * The initiator index must be equal to the VCI SRCID value. Most hardware interconnects (such
     37   as the [wiki:Component/PibusBcu PibusBcu] or the [wiki:Component/VciVgmn VciVgmn] components)
     38   make the assumption that the initiator indexes are between 0 and M -1 , where M is the total number of VCI initiators.
    3739 * The VCI ADDRESS field is structured in two fields:  | MSB | OFFSET |
    3840   * The MSB field is decoded by the flat interconnect to route the command packet to the proper VCI target.
    3941   * The OFFSET field is decoded by the VCI target.
    4042 * The VCI SRCID field is used by the interconnect to route the response packet to the proper VCI initiator.
    41  * Most flat hardware interconnects (such as the PibusBcu or the VciVgmn components) make the assumption that the target indexes are between 0 and T -1 (where T is the total number of VCI targets), and the initiator indexes are between 0 and M -1 (where M is the total number of VCI initiators).
     43 * Most flat hardware interconnects (such as the [wiki:Component/PibusBcu PibusBcu] or the
     44   [wiki:Component/VciVgmn VciVgmn] components) make the assumption that the target indexes are
     45   between 0 and T -1 (where T is the total number of VCI targets), and the initiator indexes are between
     46   0 and M -1 (where M is the total number of VCI initiators).
    4247
    4348Therefore, the flat interconnect must contain a ROM implementing a '''routing table''' indexed by the
    … …  
    6772
    6873The services provided by the Mapping Table for a two level interconnect are the following :
    69  * It generates the '''Global Routing Table''', indexed by the VCI ADDRESS MSB bits, and containing the corresponding global index (cluster index). This Global Routing Table is used by the global interconnect.
    70  * It generates - for each cluster - the '''Local Routing Table''', indexed by the VCI ADDRESS LSB bits and containing the corresponding target local index. Depending on the mapping, each cluster can have a different Local Routing Table.
     74 * It generates the '''Global Routing Table''', indexed by the VCI ADDRESS MSB bits, and containing
     75   the corresponding global index (cluster index). This Global Routing Table is used by the global interconnect.
     76 * It generates - for each cluster - the '''Local Routing Table''', indexed by the VCI ADDRESS LSB bits
     77   and containing the corresponding target local index. Depending on the mapping, each cluster can
     78   have a different Local Routing Table.
     79
     80