Changes between Version 6 and Version 7 of Component/Mapping Table


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Timestamp:
Feb 10, 2008, 5:18:06 PM (17 years ago)
Author:
alain
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  • Component/Mapping Table

    v6 v7  
    11[wiki:Component SocLib Components General Index]
    22
    3 = !MappingTable Functional Description =
     3= !MappingTable =
     4
     5== 1) Functional Description ==
    46
    57This object is NOT an hardware component. It can be used by the system designer to describe
    … …  
    1315
    1416From this centralized description, it is possible to derive the '''routing tables''' used by the
    15 hardware interconnect to decode the VCI address, and route the VCI packets to the proper target.
     17hardware interconnect components to decode the VCI address, and route the VCI packets to
     18the proper VCI target.
    1619
    1720All VCI initiators and VCI targets share the same  address space, but the address decoding
    1821scheme can support a structured interconnect.
    1922
    20 = Usage =
     23== 2) Usage ==
    2124
    22 == Mapping Table ==
     25=== mapping table instanciation ===
    2326
    24 Mapping table must know:
    25  * The address width
    26  * The number interconnection levels (most of the time 1 or 2)
    27  * The widths of the address subfields used for command routing
    28  * The widths of the RSRCID subfields used for response routing
     27The mapping table must define :
     28 * The address width (number of bits)
     29 * The number interconnection levels, defining the number of address subfields to be decoded.
     30 * The widths of the address subfields used for command packets routing
     31 * The widths of the RSRCID subfields used for response packet routing
    2932 * The mask used in XCache for determining if an address is cacheable or not
    30 
    31 The number of interconnection levels is implicit by the length of lists of subfields lengths.
    32 
    33 MappingTable instanciation is:
    3433
    3534{{{
    … …  
    45448 address bits for global command routing, 4 address bits for local command routing,
    46458 RSRCID bits for global response routing, 2 RSRCID bits for local response routing.
    47 This makes RSRCID field 10-bit wide, this should be enforced.
     46This makes RSRCID field 10-bit wide.
    4847
    49 == Segments ==
     48=== Segments definition ===
    5049
    51 Segments holds information about a portion of addressable memory region, with some attributes:
     50Segments holds information about a portion of the address space, with some attributes:
    5251 * a name
    5352 * a base address
    … …  
    5857The size field is a number of bytes. The target_index field identifies the VCI target that contains
    5958the corresponding segment, and is used by the interconnect to route a command packet to the proper target.
    60 The cacheability field can be used by the cache controllers to define if the corresponding segment is cacheable.
     59The cacheability field is used by the [wiki:Component/VciXcache VciXcache] component to define if the corresponding segment is cacheable. All segments defined by the system designer for a given architecture must be non-overlaping.
    6160
    62 All segments defined by the system designer for a given architecture must be non-overlaping.
    63 
    64 A Segment instanciation is:
    65 {{{
    66 Segment( name, base_address, size, target, cacheable )
    67 }}}
    68 
    69 For instance:
    70 {{{
    71 Segment( "seg0", 0x50000, 0x1000, IntTab(3,2), true )
    72 }}}
    73 
    74 This segment is associated to target on port 2 in cluster no 3. It is cacheable.
    75 
    76 It can be added in MappingTable with the method add():
     61A segment can be added in the mapping table with the method add():
    7762{{{
    7863maptab.add(Segment( "seg0", 0x50000, 0x1000, IntTab(3,2), true ))
    7964}}}
    8065
    81 For each new segment added, the mapping table will ensure the segments are not overlapping.
     66This segment is associated to target no 2 in cluster no 3. It is cacheable.
    8267
    83 == Cacheability ==
     68=== Cacheability ===
    8469
    85 Cacheability is a by-segment attribute. It is associated to the address. Here, "seg0" is at address 0x50000, and cacheability mask is
    86 0xc0000, resulting cacheability-determining-address is `0x50000 & 0xc0000 = 0x40000`. Now, for any other address matching
    87 `address & 0xc0000 = 0x40000`, cacheability will be true. This will be enforced by mapping_table or you'll get an `"Incoherent MappingTable" exception`.
     70Cacheability is a by-segment attribute. All addresses in all cacheable segments define 
     71a unique ''cacheability mask'', that is used by
     72the [wiki:Component/VciXcache VciXcache] component to determine the cacheability.
     73This will be checked by the mapping table, or you'll get an `"Incoherent MappingTable" exception`.
    8874
    89 = Interconnection examples =
     75== 3) examples ==
    9076
    91 == One level interconnect ==
     77=== One level interconnect ===
    9278
    9379This is the simplest case, where all VCI targets and VCI initiators are connected to a "flat" interconnect.
    … …  
    11197The content of this '''routing table''' is automatically computed by a method associated to the mapping table.
    11298
    113 == Two-level interconnect ==
     99=== Two-level interconnect ===
    114100
    115101With a two-level interconnect, the hardware architecture is supposed to be split into several subsystems
    … …  
    137123   have a different Local Routing Table.
    138124
    139 == More levels ==
    140 
    141 You may imagine those schemes are extensible to arbitrary level of interconnexion. The current !MappingTable, with
    142 the help of `IntTab`s, is not limited.
    143