Changes between Version 9 and Version 10 of Component/Mips


Ignore:
Timestamp:
Sep 25, 2007, 10:49:58 AM (18 years ago)
Author:
Nicolas Pouillon
Comment:

Sync doc with ISS

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  • Component/Mips

    v9 v10  
    33= Mips Processor Functional Description =
    44
    5 This hardware component is a Mips R3000 processor core.
    6 This uses the generic [wiki:Component/VciXcache VciXcache] component to interface
    7 a VCI advanced interconnect.
     5This hardware component is a Mips R3000 processor core. This is only an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper].
    86
    9 The simulation model is actually an instruction set simulator (ISS),
    10 organised as a three-stage pipeline:
     7The simulation model is actually an instruction set simulator, organised as a three-stage pipeline:
    118 * First stage: instruction fetch, with access to the external instruction cache.
    129 * Second stage: instruction is executed with a possible access to the external data cache.
    … …  
    3633
    3734The caba implementation is in
    38  * source:trunk/soclib/systemc/include/caba/processor/mips.h
    39  * source:trunk/soclib/systemc/src/caba/processor/mips.cc
    40  * source:trunk/soclib/systemc/src/caba/processor/mips_jumps.cc
    41  * source:trunk/soclib/systemc/src/caba/processor/mips_special.cc
    42  * source:trunk/soclib/systemc/src/caba/processor/mips_decod.cc
     35 * source:trunk/soclib/systemc/include/common/iss/mips.h
     36 * source:trunk/soclib/systemc/src/common/iss/mips.cc
     37 * source:trunk/soclib/systemc/src/common/iss/mips_instructions.cc
    4338
    4439== Template parameters ==
    … …  
    6964== Ports ==
    7065
    71  * sc_in<bool> '''p_resetn''' : Global system reset
    72  * sc_in<bool> '''p_clk''' : Global system clock
    73  * sc_in<bool> '''p_irq![6]''' : The interrupts
    74  * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the [wiki:Component/VciXcache VciXcache]
    75  * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the [wiki:Component/VciXcache VciXcache]
     66None, it is to the wrapper to provide them.
     67