Changes between Version 13 and Version 14 of Component/Mips

Timestamp:

Jan 27, 2008, 12:47:06 PM (16 years ago)

Author:

Nicolas Pouillon

Comment:

Mips with different endiannesses

Component/Mips

@@ -19 +19 @@
    with the GPR![0] destination register, a cache line invalidation request is sent to the data cache.
 
+It exists in Big-endian and Little-endian forms.
+
 = Component definition =
 
-Available in source:trunk/soclib/desc/soclib/mips.sd
+Available in source:trunk/soclib/desc/soclib/mipsel.sd and source:trunk/soclib/desc/soclib/mipseb.sd
 
 == Usage ==
@@ -27 +29 @@
 Mips has no parameters.
 {{{
-Uses( 'mips')
+Uses( 'mipsel')
+}}}
+or
+{{{
+Uses( 'mipseb')
 }}}
 
@@ -42 +48 @@
 
 == Constructor parameters ==
+
 {{{
-MipsIss( 
+MipsElIss( 
      sc_module_name name,   //  Instance Name
      int  ident);   // processor id
+}}}
+or
+{{{
+MipsEbIss( name, ident);
 }}}