Changes between Version 18 and Version 19 of Component/Mips


Ignore:
Timestamp:
Aug 14, 2008, 11:07:37 PM (16 years ago)
Author:
alain
Comment:

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  • Component/Mips

    v18 v19  
    1313 * LWL/LWR instructions are not yet implemented even if patent expired on 2006-12-23 ([http://jonahprobell.com/lexra.html source])
    1414 * The floating point instructions are not supported
    15  * There is no TLB, and no hardware support for virtual memory
     15 * There is no TLB, and no hardware support for virtual memory, as a generic MMU is implemented
     16   in the [wiki:Component/VciVcacheWrapper VciVcacheWrapper] component.
    1617 * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE,
    1718   but the write errors are not precise, due to the posted write buffer in the cache controller.