Changes between Version 1 and Version 2 of Component/Mips

Timestamp:

May 6, 2007, 2:26:06 PM (18 years ago)

Author:

alain

Comment:

--

Component/Mips

@@ -9 +9 @@
 The simulation model is actually an instruction set simulator (ISS),
 organised as a two-stage pipeline:
- * The first pipeline stage is the instruction fetch, with access to the external instruction cache
- * The second pipeline stage is the instruction execution; with a possible access to the external data cache
+ * TIn the first cycle, the instruction fetch, with access to the external instruction cache.
+ * In the second cycle, the instruction is executed with a possible access to the external data cache.
  * The "delayed branch" is accurately modelized, but not the "delayed load".
 The main functional specifications are the following:
@@ -16 +16 @@
  * There is no TLB : no hardware support for virtual memory
  * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE, but the write errors are not precise, due to the posted write buffer in the cache controller.
- * Five "system registers" are defined :
+ * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the R0 destination register, a cache line invalidation request is sent to the data cache.
 
- 
 = Mips Processor  CABA  Implementation =
 
 The caba implementation is in 
- * source:trunk/soclib/systemc/include/caba/interconnect/pibus_bcu.h
- * source:trunk/soclib/systemc/src/caba/interconnect/pibus_bcu.cc
+ * source:trunk/soclib/systemc/include/caba/processor/Mips.h
+ * source:trunk/soclib/systemc/src/caba/processor/Mips.cc
 
 == Template parameters ==
  
-template<typename vci_param>
+This component has no template parameters.
 
 == Constructor parameters ==
 {{{
-PiBcu( 
+Mips( 
      sc_module_name name,   //  Instance Name
-     const soclib::common::MappingTable &mp,   // Mapping Table
-     size_t nb_master,   // Number of initiators
-     size_t nb-slave,   // Number of targets
-     uint32_t time_out);   // Time-out (number of cycles)
+     int  ident);   // processor id
 }}}
+
+== Visible registers ==
+
+ The following internal registers define the processor internal state, and can be inspected:
+ * PC : program counter
+ * IR : Instruction register
+ * GR[i] : General registers ( 0 < i < 32)
+ * HI & LO : intermediate registers for multiply / divide instructions
+ * IDENT : processor id register  = CP0[0]
+ * BAR : Bad address register  = CP0[8]
+ * SR : Status register = CP0[12]
+ * CR : Cause register = CP0[13]
+ * EPC : Exception PC register = CP0[14]
 
 == Ports ==