Changes between Version 2 and Version 3 of Component/Mips

Timestamp:

May 6, 2007, 2:28:51 PM (18 years ago)

Author:

alain

Comment:

--

Component/Mips

@@ -9 +9 @@
 The simulation model is actually an instruction set simulator (ISS),
 organised as a two-stage pipeline:
- * TIn the first cycle, the instruction fetch, with access to the external instruction cache.
+ * In the first cycle, the instruction fetch, with access to the external instruction cache.
  * In the second cycle, the instruction is executed with a possible access to the external data cache.
- * The "delayed branch" is accurately modelized, but not the "delayed load".
 The main functional specifications are the following:
  * The floating point instructions are not supported
@@ -21 +20 @@
 
 The caba implementation is in 
- * source:trunk/soclib/systemc/include/caba/processor/Mips.h
- * source:trunk/soclib/systemc/src/caba/processor/Mips.cc
+ * source:trunk/soclib/systemc/include/caba/processor/mips.h
+ * source:trunk/soclib/systemc/src/caba/processor/mips.cc
 
 == Template parameters ==