Changes between Version 3 and Version 4 of Component/Mips

Timestamp:

May 6, 2007, 2:30:32 PM (18 years ago)

Author:

alain

Comment:

--

Component/Mips

@@ -15 +15 @@
  * There is no TLB : no hardware support for virtual memory
  * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE, but the write errors are not precise, due to the posted write buffer in the cache controller.
- * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the R0 destination register, a cache line invalidation request is sent to the data cache.
+ * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the GR[0] destination register, a cache line invalidation request is sent to the data cache.
 
 = Mips Processor  CABA  Implementation =