Changes between Version 4 and Version 5 of Component/Mips


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Timestamp:
May 6, 2007, 2:31:07 PM (17 years ago)
Author:
alain
Comment:

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  • Component/Mips

    v4 v5  
    1313The main functional specifications are the following:
    1414 * The floating point instructions are not supported
    15  * There is no TLB : no hardware support for virtual memory
     15 * There is no TLB, and no hardware support for virtual memory
    1616 * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE, but the write errors are not precise, due to the posted write buffer in the cache controller.
    17  * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the GR[0] destination register, a cache line invalidation request is sent to the data cache.
     17 * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the GR![0] destination register, a cache line invalidation request is sent to the data cache.
    1818
    1919= Mips Processor  CABA  Implementation =