Changes between Version 6 and Version 7 of Component/Mips

Timestamp:

May 9, 2007, 1:29:42 PM (18 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Mips

@@ -39 +39 @@
  * PC : Program counter
  * IR : Instruction register
- * GR[i] : General registers ( 0 < i < 32)
+ * GPR[i] : General registers ( 0 < i < 32)
  * HI & LO : Intermediate registers for multiply / divide instructions
- * IDENT : Processor id register  = CP0[0]
- * BAR : Bad address register  = CP0[8]
- * SR : Status register = CP0[12]
- * CR : Cause register = CP0[13]
- * EPC : Exception PC register = CP0[14]
+ * CP0_REG[i] : Coprocessor 0 registers (0<=i<32). Implemented values:
+  * BAR : Bad address register  = CP0![8]
+  * SR : Status register = CP0![12]
+  * CR : Cause register = CP0![13]
+  * EPC : Exception PC register = CP0![14]
+  * INFOS : CP0![15] with CPU identification number on bits ![9:0]
 
 == Ports ==
@@ -51 +52 @@
  * sc_in<bool> '''p_resetn''' : Global system reset
  * sc_in<bool> '''p_clk''' : Global system clock
- * sc_in<bool> '''*p_irq[6]''' : The six interrupt requests 
- * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the VciXcache 
- * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the VciXcache
+ * sc_in<bool> '''p_irq[6]''' : The interrupts
+ * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the [wiki:Component/VciXcache VciXcache]
+ * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the [wiki:Component/VciXcache VciXcache]