Changes between Version 6 and Version 7 of Component/Mips
- Timestamp:
- May 9, 2007, 1:29:42 PM (17 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
Component/Mips
v6 v7 39 39 * PC : Program counter 40 40 * IR : Instruction register 41 * G R[i] : General registers ( 0 < i < 32)41 * GPR[i] : General registers ( 0 < i < 32) 42 42 * HI & LO : Intermediate registers for multiply / divide instructions 43 * IDENT : Processor id register = CP0[0] 44 * BAR : Bad address register = CP0[8] 45 * SR : Status register = CP0[12] 46 * CR : Cause register = CP0[13] 47 * EPC : Exception PC register = CP0[14] 43 * CP0_REG[i] : Coprocessor 0 registers (0<=i<32). Implemented values: 44 * BAR : Bad address register = CP0![8] 45 * SR : Status register = CP0![12] 46 * CR : Cause register = CP0![13] 47 * EPC : Exception PC register = CP0![14] 48 * INFOS : CP0![15] with CPU identification number on bits ![9:0] 48 49 49 50 == Ports == … … 51 52 * sc_in<bool> '''p_resetn''' : Global system reset 52 53 * sc_in<bool> '''p_clk''' : Global system clock 53 * sc_in<bool> ''' *p_irq[6]''' : The six interrupt requests54 * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the VciXcache55 * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the VciXcache54 * sc_in<bool> '''p_irq[6]''' : The interrupts 55 * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the [wiki:Component/VciXcache VciXcache] 56 * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the [wiki:Component/VciXcache VciXcache]
