Changes between Version 7 and Version 8 of Component/Mips


Ignore:
Timestamp:
May 9, 2007, 4:50:24 PM (18 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Component/Mips

    v7 v8  
    44
    55This hardware component is a Mips R3000 processor core.
    6 This uses the generic [wiki:Components/VciXcache VciXcache] component to interface
     6This uses the generic [wiki:Component/VciXcache VciXcache] component to interface
    77a VCI advanced interconnect.
    88
    99The simulation model is actually an instruction set simulator (ISS),
    10 organised as a two-stage pipeline:
    11  * In the first cycle, the instruction fetch, with access to the external instruction cache.
    12  * In the second cycle, the instruction is executed with a possible access to the external data cache.
     10organised as a three-stage pipeline:
     11 * First stage: instruction fetch, with access to the external instruction cache.
     12 * Second stage: instruction is executed with a possible access to the external data cache.
     13 * Third stage: read memory access is written back to registers
     14
    1315The main functional specifications are the following:
     16 * The patented LWL/LWR instructions are not implemented
    1417 * The floating point instructions are not supported
    1518 * There is no TLB, and no hardware support for virtual memory
    16  * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE, but the write errors are not precise, due to the posted write buffer in the cache controller.
    17  * A data cache line invalidation mechanism is supported : when a ''lw'' instruction is executed with the GR![0] destination register, a cache line invalidation request is sent to the data cache.
     19 * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE,
     20   but the write errors are not precise, due to the posted write buffer in the cache controller.
     21 * A data cache line invalidation mechanism is supported: when a ''LW'' instruction is executed
     22   with the GPR![0] destination register, a cache line invalidation request is sent to the data cache.
    1823
    1924= Mips Processor  CABA  Implementation =
    … …  
    2227 * source:trunk/soclib/systemc/include/caba/processor/mips.h
    2328 * source:trunk/soclib/systemc/src/caba/processor/mips.cc
     29 * source:trunk/soclib/systemc/src/caba/processor/mips_jumps.cc
     30 * source:trunk/soclib/systemc/src/caba/processor/mips_special.cc
     31 * source:trunk/soclib/systemc/src/caba/processor/mips_decod.cc
    2432
    2533== Template parameters ==
    … …  
    4250 * HI & LO : Intermediate registers for multiply / divide instructions
    4351 * CP0_REG[i] : Coprocessor 0 registers (0<=i<32). Implemented values:
    44   * BAR : Bad address register  = CP0![8]
    45   * SR : Status register = CP0![12]
    46   * CR : Cause register = CP0![13]
    47   * EPC : Exception PC register = CP0![14]
    48   * INFOS : CP0![15] with CPU identification number on bits ![9:0]
     52  *  8: BAR : Bad address register
     53  * 12: SR : Status register
     54  * 13: CR : Cause register
     55  * 14: EPC : Exception PC register
     56  * 15: INFOS : CPU identification number on bits ![9:0]
    4957
    5058== Ports ==
    … …  
    5260 * sc_in<bool> '''p_resetn''' : Global system reset
    5361 * sc_in<bool> '''p_clk''' : Global system clock
    54  * sc_in<bool> '''p_irq[6]''' : The interrupts
     62 * sc_in<bool> '''p_irq![6]''' : The interrupts
    5563 * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the [wiki:Component/VciXcache VciXcache]
    5664 * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the [wiki:Component/VciXcache VciXcache]