Changes between Version 8 and Version 9 of Component/Mips


Ignore:
Timestamp:
May 17, 2007, 11:33:31 AM (18 years ago)
Author:
Nicolas Pouillon
Comment:

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  • Component/Mips

    v8 v9  
    2121 * A data cache line invalidation mechanism is supported: when a ''LW'' instruction is executed
    2222   with the GPR![0] destination register, a cache line invalidation request is sent to the data cache.
     23
     24= Component definition =
     25
     26Available in source:trunk/soclib/desc/soclib/mips.sd
     27
     28== Usage ==
     29
     30Mips has no parameters.
     31{{{
     32Uses( 'mips')
     33}}}
    2334
    2435= Mips Processor  CABA  Implementation =