[wiki:Component SocLib Components General Index] 

= Mips Processor Functional Description =

This hardware component is a Mips R3000 processor core.
This uses the generic [wiki:Components/VciXcache VciXcache] component to interface
a VCI advanced interconnect.

The simulation model is actually an instruction set simulator (ISS),
organised as a two-stage pipeline:
 * The first pipeline stage is the instruction fetch, with access to the external instruction cache
 * The second pipeline stage is the instruction execution; with a possible access to the external data cache
 * The "delayed branch" is accurately modelized, but not the "delayed load".
The main functional specifications are the following:
 * The floating point instructions are not supported
 * There is no TLB : no hardware support for virtual memory
 * All Mips R3000 exceptions are handled, including the memory addressing X_IBE and X_DBE, but the write errors are not precise, due to the posted write buffer in the cache controller.
 * Five "system registers" are defined :

 
= Mips Processor  CABA  Implementation =

The caba implementation is in 
 * source:trunk/soclib/systemc/include/caba/interconnect/pibus_bcu.h
 * source:trunk/soclib/systemc/src/caba/interconnect/pibus_bcu.cc

== Template parameters ==
 
template<typename vci_param>

== Constructor parameters ==
{{{
PiBcu( 
     sc_module_name name,   //  Instance Name
     const soclib::common::MappingTable &mp,   // Mapping Table
     size_t nb_master,   // Number of initiators
     size_t nb-slave,   // Number of targets
     uint32_t time_out);   // Time-out (number of cycles)
}}}

== Ports ==

 * sc_in<bool> '''p_resetn''' : Global system reset
 * sc_in<bool> '''p_clk''' : Global system clock
 * sc_in<bool> '''*p_irq[6]''' : The six interrupt requests 
 * soclib::caba::!IcacheProcesssorPort '''p_icache''' : Instruction cache interface to the VciXcache 
 * soclib::caba::!DcacheProcesssorPort '''p_dcache''' : Data cache interface to the VciXcache