| | 1 | [wiki:Component SocLib Components General Index] |
| | 2 | |
| | 3 | = NiosII Processor Functional Description = |
| | 4 | |
| | 5 | This hardware component belongs to the NiosII embedded processor family designed for Altera® field programmable gate array (FPGA) devices. The NiosII processor is a configurable soft-core processor, as opposed to a fixed, off-the-shelf processor. “Configurable” means that features can be added or removed on a system-by-system basis to meet performance goals. Altera® offers three NiosII cores: |
| | 6 | * NiosII/f. The NiosII/f “fast” core is designed for fast performance. |
| | 7 | * NiosII/s. The NiosII/s “standard” core is designed for small size while maintaining performance. |
| | 8 | * NiosII/e. The NiosII/e “economy” core is designed to achieve the smallest possible core size. |
| | 9 | This hardware component is only an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper]. |
| | 10 | |
| | 11 | The simulation model is actually an instruction set simulator, organized as a three-stage pipeline: |
| | 12 | * First stage: instruction fetch, with access to the external instruction cache. |
| | 13 | * Second stage: instruction is executed with a possible access to the external data cache. |
| | 14 | * Third stage: read memory access is written back to registers |
| | 15 | |
| | 16 | This component models the NiosII/f “fast” core. Its main functional specifications are the following: |
| | 17 | * Hardware multiplication and division are supported |
| | 18 | * Floating-point instructions are supported by the way of custom instructions |
| | 19 | * dynamic branch prediction is not supported |
| | 20 | * optional tightly-coupled memory for instructions and data is not supported |
| | 21 | * Load and store I/O instructions are not supported |
| | 22 | |
| | 23 | = Component definition = |
| | 24 | |
| | 25 | Available in source:trunk/soclib/desc/soclib/nios2_fast.sd |
| | 26 | |
| | 27 | = Usage = |
| | 28 | |
| | 29 | NiosII has no parameters. |
| | 30 | {{{ |
| | 31 | Uses( 'nios2_fast') |
| | 32 | }}} |
| | 33 | |
| | 34 | = NiosII Processor ISS Implementation = |
| | 35 | |
| | 36 | The implementation is in |
| | 37 | * source:trunk/soclib/systemc/include/common/iss/nios2_fast.h |
| | 38 | * source:trunk/soclib/systemc/src/common/iss/nios2_fast.cc |
| | 39 | * source:trunk/soclib/systemc/src/common/iss/nios2_fast_itype_instructions.cc |
| | 40 | * source:trunk/soclib/systemc/src/common/iss/nios2_fast_rtype_instructions.cc |
| | 41 | * source:trunk/soclib/systemc/src/common/iss/nios2_fast_custom_instructions.cc |
| | 42 | |
| | 43 | == Template parameters == |
| | 44 | |
| | 45 | This component has no template parameters. |
| | 46 | |
| | 47 | == Constructor parameters == |
| | 48 | {{{ |
| | 49 | Nios2fIss( |
| | 50 | sc_module_name name, // Instance Name |
| | 51 | int ident); // processor id |
| | 52 | }}} |
| | 53 | |
| | 54 | == Visible registers == |
| | 55 | |
| | 56 | |
| | 57 | The following internal registers define the processor internal state, and can be inspected: |
| | 58 | * r_pc : Program counter |
| | 59 | * m_instruction : Instruction register |
| | 60 | * r_gpr[i] : General-purpose registers ( 0 < i < 32) |
| | 61 | * r_ctr[i] : Control registers ( 0 < i < 6) |
| | 62 | * |
| | 63 | * |
| | 64 | == Interrupts == |
| | 65 | |
| | 66 | NiosII defines 32 interrupt-request inputs. The lowest number has the highest priority. |
| | 67 | |
| | 68 | == Ports == |
| | 69 | |
| | 70 | None, it is to the wrapper to provide them. |
