Changes between Version 2 and Version 3 of Component/TMS320C62


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Timestamp:
Feb 11, 2009, 9:58:47 AM (15 years ago)
Author:
irisa
Comment:

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  • Component/TMS320C62

    v2 v3  
    33= TMS320C62 Processor Functional Description =
    44
    5 This hardware component
    6  
    7 This hardware component is only an ISS, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper].
     5This hardware component is a TMS320C62x core. The main features of the C62x CPU include:
     6 * VLIW CPU with eight functional units, including two multipliers and six arithmetic units
     7 * Instruction packing
     8 * Conditional execution of all instructions
    89
     10All instructions in the C62x DSP instruction set flow through the fetch, decode and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction. The pipeline can dispatch eight parallel instructions every cycle. Parallel instructions proceed simultaneously through each pipeline phase. Serial instructions proceed through the pipeline with a fixed relative phase difference between instructions.
     11
     12This hardware component is an instruction set simulator, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper]-like wrapper, compatible with the cache interface defined by the [wiki:Component/VciXcache VciXcache] component. A IssC6xWrapper, adapted to the features of the C62x model is proposed.
     13
     14It implements all instructions defined in the C62x architecture specification, with the following limitations:
     15 * the C62x has internal (on-chip) memory, organized in separate data and program spaces, this feature is not supported
    916
    1017= Component definition =
    … …  
    4047}}}
    4148
    42 == Visible registers ==
    43 
    44 
    45     The following internal registers define the processor internal state, and can be inspected:
    46 
    4749
    4850== Interrupts ==
    … …  
    5254
    5355None, it is to the wrapper to provide them.
     56
     57= Compiling programs for TMS320C62 with !SoClib =
     58
     59Free downloads of Texas Instruments Code Generation Tools for TMS320C6000 instruction set architectures produced by TI are available [https://www-a.ti.com/downloads/sds_support/targetcontent/LinuxDspTools/download.html]. These evaluation tools run on Linux x86 hosts.
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