Changes between Version 4 and Version 5 of Component/TMS320C62


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Timestamp:
May 11, 2009, 11:40:45 AM (16 years ago)
Author:
irisa
Comment:

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  • Component/TMS320C62

    v4 v5  
    1010All instructions in the C62x DSP instruction set flow through the fetch, decode and execute stages of the pipeline. The fetch stage of the pipeline has four phases for all instructions and the decode stage has two phases for all instructions. The execute stage of the pipeline requires a varying number of phases, depending on the type of instruction. The pipeline can dispatch eight parallel instructions every cycle. Parallel instructions proceed simultaneously through each pipeline phase. Serial instructions proceed through the pipeline with a fixed relative phase difference between instructions.
    1111
    12 This hardware component is an instruction set simulator, which should be wrapped with an [wiki:Component/IssWrapper IssWrapper]-like wrapper, compatible with the cache interface defined by the [wiki:Component/VciXcache VciXcache] component. A IssC6xWrapper, adapted to the features of the C62x model is proposed.
     12This hardware component is only an ISS, which should be wrapped with a CABA or TLM-T [wiki:Component/VciXcacheWrapper Wrapper] using the [wiki:Component/IssIss2 IssIss2] utility component.
    1313
    1414It implements all instructions defined in the C62x architecture specification, with the following limitations: