| 1 | [wiki:Component SocLib Components General Index] |
| 2 | |
| 3 | = Tc1700 = |
| 4 | |
| 5 | == 1) Functional Description == |
| 6 | |
| 7 | This TC1700 is a flexible turbo decoder covering WiMAX, LTE and HSPA+ specifications provided by [http://www.turboconcept.com TurboConcept]. Full documentation is available online at [http://www.turboconcept.com/prod_tc1700.php TurboConcept's Web Site]. |
| 8 | |
| 9 | !TurboConcept's TC1700 Core is a turbo decoder that supports three PHY layer specifications: |
| 10 | * 3GPP-HSPA |
| 11 | * 3GPP-LTE |
| 12 | * WiMAX IEEE802.16e |
| 13 | The Core is optimized for ASIC and FPGA target and uses a unique architecture that reduces by more than 50 % the silicon area when compared to separate single-mode Cores, with no restrictions on the flexibility and features set. |
| 14 | |
| 15 | |
| 16 | [[Image(tc1700.png,align=top,nolink, title=Figure 1 - Tc1700)]] |
| 17 | |
| 18 | Figure 1 presents the general core structure. The Tc1700 is connected to a MWMR wrapper in order to interface the core to the MWMR controller available at [wiki:Component/VciMwmrController VciMwmrController]. |
| 19 | |
| 20 | == 2) CABA Implementation == |
| 21 | |
| 22 | == a) Component definition & usage == |
| 23 | |
| 24 | * source:trunk/soclib/soclib/module/streaming_component/tc1700/caba/metadata/tc1700.sd |
| 25 | * source:trunk/soclib/binary/module/streaming_component/tc1700/caba/doc |
| 26 | |
| 27 | |
| 28 | == b) CABA sources == |
| 29 | |
| 30 | * interface : source:trunk/soclib/soclib/module/streaming_component/tc1700/caba/source/include/tc1700.h |
| 31 | * implementation : source:trunk/soclib/soclib/module/streaming_component/tc1700/caba/source/src/tc1700.cpp |
| 32 | * internal component interface : source:trunk/soclib/binary/module/streaming_component/tc1700/caba/include/tc_tc1700.h |
| 33 | * internal component library : source:trunk/soclib/binary/module/streaming_component/tc1700/caba/lib |
| 34 | |
| 35 | |
| 36 | === CABA Constructor parameters === |
| 37 | |
| 38 | * TC1700 decoder |
| 39 | {{{ |
| 40 | Tc1700( |
| 41 | sc_module_name name) // Instance name |
| 42 | }}} |
| 43 | |
| 44 | |
| 45 | === CABA Ports === |
| 46 | * sc_in<bool> '''p_resetn''' : hardware reset |
| 47 | * sc_in<bool> '''p_clk''' : clock |
| 48 | * soclib::caba::!FifoOutput<uint32_t> '''p_tc1700_to_MWMR''' : interface from the tc1700 to the MWMR controller |
| 49 | * soclib::caba::!FifoInput<uint32_t> '''p_MWMR_to_tc1700''' : interface from the MWMR controller to the tc1700 |
| 50 | |
| 51 | |
| 52 | == 3) TLM-DT Implementation == |
| 53 | |
| 54 | == a) Component definition & usage == |
| 55 | |
| 56 | * source:trunk/soclib/soclib/module/streaming_component/tc1700/tlmdt/metadata/tc1700.sd |
| 57 | * source:trunk/soclib/binary/module/streaming_component/tc1700/tlmdt/doc |
| 58 | |
| 59 | === TLM-DT sources === |
| 60 | |
| 61 | * interface : source:trunk/soclib/soclib/module/streaming_component/tc1700/tlmdt/source/include/tc1700.h |
| 62 | * implementation : source:trunk/soclib/soclib/module/streaming_component/tc1700/tlmdt/source/src/tc1700.cpp |
| 63 | * internal component interface : source:trunk/soclib/binary/module/streaming_component/tc1700/tlmdt/include/tc_tc1700.h |
| 64 | * internal component library : source:trunk/soclib/binary/module/streaming_component/tc1700/tlmdt/lib |
| 65 | |
| 66 | === TLM-DT Constructor parameters === |
| 67 | {{{ |
| 68 | Tc1700( |
| 69 | sc_module_name name, // Instance name |
| 70 | uint32_t id, |
| 71 | uint32_t MWMR2core_fifo_depth, |
| 72 | uint32_t core2MWMR_fifo_depth) |
| 73 | }}} |
| 74 | |
| 75 | === TLM-DT Ports === |
| 76 | * std::vector<tlm_utils::simple_target_socket_tagged<Tc1700,32,tlm::tlm_base_protocol_types> *> '''p_config''': configuration port |
| 77 | * std::vector<tlm_utils::simple_target_socket_tagged<Tc1700,32,tlm::tlm_base_protocol_types> *> '''p_status''': status port |
| 78 | * std::vector<tlm_utils::simple_initiator_socket_tagged<Tc1700,32,tlm::tlm_base_protocol_types> *> '''p_read_fifo''': port from the MWMR controller to the Tc1700 |
| 79 | * std::vector<tlm_utils::simple_initiator_socket_tagged<Tc1700,32,tlm::tlm_base_protocol_types> *> '''p_write_fifo''': port from the Tc1700 to the MWMR controller |
| 80 | |
| 81 | |
| 82 | |
| 83 | == 4) Limitation == |
| 84 | |
| 85 | This model has the following limitations: |
| 86 | * fixed number of performed iterations. |
| 87 | |
| 88 | The number of performed iterations is fixed to a reasonable value still offering close-to-ideal Bit Error Rate (BER) performances. Please contact [http://www.turboconcept.com TurboConcept] for information about these limitations. |
| 89 | |
| 90 | == 5) License == |
| 91 | |
| 92 | The MWMR wrapper is licensed under the SoCLib, GNU LGPLv2.1 license. |
| 93 | |
| 94 | The MWMR wrapper instantiates an internal hardware decoder. This internal hardware decoder is licensed under BSD-like license. |
| 95 | |
| 96 | This internal hardware decoder is distributed in a binary form. |
| 97 | |
| 98 | == 6) RTL model == |
| 99 | |
| 100 | Please contact [http://www.turboconcept.com TurboConcept] for information about purchasing a fully functional RTL model of the internal hardware decoder. |