Changes between Initial Version and Version 1 of Component/Vci Ahci Sdc


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Timestamp:
Apr 28, 2015, 8:09:37 PM (9 years ago)
Author:
alain
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  • Component/Vci Ahci Sdc

    v1 v1  
     1[wiki:Component SocLib Components General Index]
     2
     3= !VciAhciSdc =
     4
     5== 1) Functional Description ==
     6
     7This component is a single channel SD card controller. From the software point of view, it respect the AHCI standard. On the physical side, it respect the 4bits SD card interface. It can be connected to the !SdCard component, that is modeled as a single file stored on the host system, and containing a complete disk image. The block size is fixed to 512 bytes.
     8The VCI burst size is an hardware parameters, defined as a constructor parameter.
     9
     10According to the AHCI specification, the controller uses a private ''Command List'' that is handled as a software FIFO, and can register up to 32 ''read'' or ''write'' commands. It uses it's DMA capability, to access both the ''Command List'' and to transfer the data to or from memory.
     11
     12On the VCI side, it supports both 32 bits and 64 bits data words, and up to 64 bits address width.
     13
     14An IRQ can be (optionally) asserted as soon as one command in the Command List is completed.
     15
     16This hardware component checks for segmentation violation, and can be used as a default target.
     17
     18== 2) Command List ==
     19
     20For each channel, the driver must use a software FIFO to register a command: The Command Descriptor array (32 entries) define the Command List. Each Command Descriptor occupies 16 bytes, and must be aligned on a 16 bytes boundary. It contains mainly the physical address of the associated Command Table. A command Descriptor is defined by the following C structure:
     21
     22{{{
     23typedef struct hba_cmd_desc_s  // size = 16 bytes
     24{
     25    unsigned char       flag[2];        // WRITE when bit 6 of flag[0] is set
     26    unsigned char       prdtl[2];       // Number of buffers
     27    unsigned int        prdbc;          // Number of bytes actually transfered
     28    unsigned int        ctba;           // Command Table base address 32 LSB bits
     29    unsigned int        ctbau;          // Command Table base address 32 MSB bits
     30} hba_cmd_desc_t;
     31}}}
     32
     33== 3) Command Table ==
     34
     35There is one Command Table for each Command descriptor. For a given command, there is one single LBA (Logic Bloc Address) on the block device, coded on 48 bits, but the source (or destination) memory buffer can be split in a variable number of contiguous buffers. Therefore, the Command Table contains two parts: a fixed size Header, defining the LBA, followed by a variable size array of fixed size buffer descriptors.
     36The Command Table describing one command is defined by the two following C structures:
     37{{{
     38
     39typedef struct hba_cmd_header_s // size = 16 bytes
     40{
     41    unsigned int       res0;        // reserved
     42    unsigned char      lba0;        // LBA 7:0
     43    unsigned char      lba1;        // LBA 15:8
     44    unsigned char      lba2;        // LBA 23:16
     45    unsigned char      res1;        // reserved
     46    unsigned char      lba3;        // LBA 31:24
     47    unsigned char      lba4;        // LBA 39:32
     48    unsigned char      lba5;        // LBA 47:40
     49    unsigned char      res1;        // reserved
     50    unsigned char      res2;        // reserved
     51    unsigned int       res3;        // reserved
     52} hba_cmd_header_t;
     53
     54typedef struct hba_cmd_buffer_s // size = 16 bytes
     55{
     56    unsigned int       dba;         // Buffer base address 32 LSB bits
     57    unsigned int       dbau;        // Buffer base address 32 MSB bits
     58    unsigned int       res0;        // reserved
     59    unsigned int       dbc;         // Buffer byte count
     60
     61} hba_cmd_buffer_t;
     62}}}
     63
     64== 4) Addressable registers ==
     65
     66Regarding the '''SD Card configuration''', this component contains three 32 bits Write-Only registers, and one 32 bits Read-Only register:
     67
     68 * '''SDC_PERIOD'''
     69This Write-Only register define the ratio between the system clock frequency and the SDC clock frequency. This ratio must be an integer value not smaller than 2.
     70
     71 * '''SDC_CMD_ARG'''
     72This 32 bits Write-Oly register must contain the argument used by the command launched by writing in the SDC_CMD_ID register.
     73
     74 * '''SDC_CMD_ID'''
     75Writing in this Write-Only register launch a command to the SD card. The command index is defined by the value written in the register. The supported commands are defined below:
     76|| Index || argument || action ||
     77|| 0     || none     || SD Card soft reset ||
     78|| 2     || none     || Request SD Card to return CID (Card Identifier) ||
     79|| 3     || none     || Request SD Card to return RCA (Relative Card Address)||
     80|| 7     || Card RCA || Toggle SD Card between "stand-by" and "transfer" states ||
     81|| 12    || Card RCA || Request SD Card to stop a multi-block data transfer||
     82|| 41    || specific || Request SD Card to return OCR (Operating Condition) ||
     83
     84 * '''SDC_STATUS'''
     85This Read-Only register contains the status of the SD Card after execution of a command launched by a write in the SDC_CMD_ID register.
     86
     87Regarding the '''AHCI configuration''', this component contains six 32 bits Read/Write registers:
     88
     89 * '''HBA_PXCLB'''
     9032 LSB bits of the Command List physical base address.
     91This address must be aligned on a 16 bytes boundary.
     92
     93 * '''HBA_PXCLBU'''
     9432 MSB bits of the Command List array physical address.
     95
     96 * '''HBA_PXIS'''
     97Channel status, used for error reporting.
     98||31||30||29||28.....24||23..........8||7.....1||0||
     99||--||R ||--|| CMD_ID  || BUFFER_ID   ||-------||D||
     100 Bit[0] : set by hardware when at least one command has been completed.
     101 Bit[30] : set by hardware when an error has been detected in a command.
     102 Bit[28:24] : index of the faulty command in command list (set by the hardware).
     103 Bit[23:8] : index of the faulty buffer in the faulty command (set by the hardware).
     104When an error is detected for a command, the R bit is set, the channel FSM stops immediately, without handling the remaining commands in the command list, and keep blocked, waiting for a software reset on this PXIS register.
     105Any write access to this register reset all bits to 0, whatever the VCI WDATA value.
     106
     107 * '''HBA_PXIE'''
     108This register enables and disables the IRQ reporting the completion (success or error) of the commands for a given channel. Only 2 bits are used:
     109||31||30||29 ...................................... 1||0||
     110||--||R ||------------------------------------||D||
     111 Bit 0 : when set, an IRQ is generated when bit0 of AHCI_PXIS is set.
     112 Bit 30 : when set, an IRQ is generated when bit30 of AHCI_PXIS is set.
     113
     114 * '''HBA_PXCMD'''
     115Boolean : Writing a non zero value activates the polling of the Command List. Writing a zero value makes a soft reset on PXCI, PXIS, PXIE, and PXCMD registers.
     116
     117 * '''HBA_PXCI'''
     118Bit-vector, one bit per command in the Command List. These bits are handled as 32 set/reset flip-flops: set by software when a command ha been posted in Command List / reset by hardware when the command is completed. A write command on this register makes a OR between the VCI WDATA field and the current value of the register.
     119
     120For extensibility issues, the software drivers must use the mnemonics defined [source:trunk/soclib/soclib/module/connectivity_component/vci_multi_ahci/include/soclib/multi_ahci.h here] to access this component .
     121
     122Even if there is only six registers per channel, each channel sub-segment occupies 4K bytes, and the HBA segment must be aligned on a 32 Kbytes boundary.
     123
     124
     125== 5) Component definition & usage ==
     126
     127source:trunk/soclib/soclib/module/connectivity_component/vci_ahci_sdc/caba/metadata/vci_ahci_sdc.sd
     128
     129
     130== 6) CABA  Implementation ==
     131
     132=== CABA sources ===
     133
     134 * interface : source:trunk/soclib/soclib/module/connectivity_component/vci_ahci_sdc/caba/source/include/vci_ahci_sdc.h
     135 * implementation : source:trunk/soclib/soclib/module/connectivity_component/vci_multi_ahci/caba/source/src/vci_ahci_sdc.cpp
     136
     137=== CABA Constructor parameters ===
     138
     139{{{
     140VciAhciSdc(
     141     sc_module_name name,   //  Component Name
     142     const soclib::common::MappingTable &mt, // MappingTable
     143     const soclib::common::IntTab &srcid,    // Initiator index
     144     const soclib::common::IntTab &tgtid,    // Target index
     145     const uint32_t burst_size ); // burst size (bytes)
     146}}}
     147
     148=== CABA Ports ===
     149
     150 * '''p_resetn''' : Global system reset
     151 * '''p_clk''' : Global system clock
     152 * '''p_vci_target''' : The VCI target port
     153 * '''p_vci_initiator''' : The VCI initiator port
     154 * '''p_channel_irq[]''' : Array of interrupt ports (one per channel)
     155
     156== 7) TLM-DT Implementation ==
     157
     158Not available yet.