| 7 | This hardware component is a generic Avalon switchfabric that interconnects ''Nb_Master'' Avalon masters and ''Nb_Slave'' Avalon slaves. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many. Masters and slaves have the same data and address widths and operate in the same clock domain. |
| 8 | |
| 9 | VCI-Avalon wrappers do not require to support full Avalon features, so not all Avalon slave and master ports are supported ([wiki:Component/AvalonSwitchMaster AvalonSwitchMaster], [wiki:Component/AvalonSwitchSlave AvalonSwitchSlave]). |
| 10 | |
| 11 | Implemented functionnalities : |
| 12 | * fundamental read, fundamental write with variable wait-state |
| 13 | * burst transfer |
| 14 | * flow control (dataavailable) |
| 15 | * round robin arbitration |