Changes between Version 2 and Version 3 of Component/Vci Avalon Bus

Timestamp:

Jan 20, 2009, 2:49:37 PM (15 years ago)

Author:

irisa

Comment:

--

Component/Vci Avalon Bus

@@ -5 +5 @@
 == 1) Functional Description ==
 
-This hardware component is a generic Avalon switchfabric that interconnects ''Nb_Master'' Avalon masters and ''Nb_Slave'' Avalon slaves. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many. Masters and slaves have the same data and address widths and  operate  in the same clock domain.
+This hardware component is a generic Avalon switchfabric allowing the interconnection of ''Nb_Master'' Avalon masters and ''Nb_Slave'' Avalon slaves. The master-to-slave relationship can be one-to-one, one-to-many, many-to-one, or many-to-many. Masters and slaves have the same data and address widths and  operate  in the same clock domain.
 
 VCI-Avalon wrappers do not require to support full Avalon features, so not all Avalon slave and master ports are supported ([wiki:Component/AvalonSwitchMaster AvalonSwitchMaster], [wiki:Component/AvalonSwitchSlave AvalonSwitchSlave]).
@@ -14 +14 @@
  * flow control (dataavailable)
  * round robin arbitration
+
+
+Unimplemented functionnalities :
+ * wait state insertion
+ * pipelined read transfers
+ * tristate transfert
+ * setup and hold time
+ * dynamic bus sizing  
+ * interrupt requests
 
 == 2) Component definition & usage ==