| | 7 | This component is a multi-channels DMA controller supporting chained buffers. |
| | 8 | It can be used to move a stream from one set of chained buffers (SRC chbuf) |
| | 9 | to another set of chained buffers (DST chbuf), without involving software. |
| | 10 | |
| | 11 | All buffers must have the same length, and must be aligned on a 32 bits word boundary. |
| | 12 | The buffer length must be the same for the SRC chbuf and for the DST chbuf. |
| | 13 | |
| | 14 | A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''. |
| | 15 | Each buffer descriptor occupies 64 bytes, but only the first 8 bytes (64 bits) contain useful information: |
| | 16 | * The 48 LSB bits contain the buffer physical address |
| | 17 | * The MSB bit 63 defines the buffer state (empty if 0) |
| | 18 | The chbuf descriptor" base address must be a multiple of 64 bytes. |
| | 19 | |
| | 20 | This DMA controller implements two mode to scan the SRC and DST chbufs: |
| | 21 | * '''IN_ORDER_FIFO''': Both the source chained buffers and the destination chained buffers are accessed in strict order, as defined by the SRC and DST chbuf descriptors. The access is blocking until the expected buffer is available. If the buffer is not available, the delay before retry is defined by the software addressable register CHBUF_PERIOD. This register must be non zero to activate this mode. |
| | 22 | * '''OUT_OF_ORDER''': The arc and DST chbuf descriptors are scanned. The first full SRC buffer found is read, and the first empty DST buffer found is written, with a round robin priority. This mode is activated when the CHBUF_PERIOD value is zero (default value). |
| | 23 | |
| | 24 | This component supports both 32 bits and 64 bits VCI RDATA & WDATA fields. |
| | 25 | |
| | 26 | The number of channels and the max burst size are constructor parameters: |
| | 27 | * The number of channels (simultaneous transfers) cannot be larger than 8. |
| | 28 | * The burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. |
| | 29 | |
| | 30 | Each channel k has 5 memory-mapped registers : |
| | 31 | * '''CHBUF_SRC[k]The chbuf descriptor address (CHBUF_DESC), and the number of chained |
| | 32 | // buffers (CHBUF_NBUFS), as well as the elementary buffer size (BUF_SIZE) |
| | 33 | // are software parameters that must be written in addressable registers |
| | 34 | // when launching a transfer between two chbufs. |
| | 35 | // |
| | 36 | // |
| | 37 | // - The elementary buffer size and all buffers base addresses must be multiple |
| | 38 | // of 4 bytes. If the source and destination buffers are not aligned on a burst |
| | 39 | // boundary, the DMA controler split the burst in two VCI transactions. |
| | 40 | // |
| | 41 | // In order to support various protection mechanisms, for each channel, |
| | 42 | // the channel addressable registers takes 4K bytes in the address space. |
| | 43 | // Only 8 address bits are decoded . |
| | 44 | // - The 5 bits ADDRESS[4:Ø] define the target register (see chbuf_dma.h) |
| | 45 | // - The 3 bits ADDRESS[14:12] define the selected channel. |
| | 46 | // |
| | 47 | |
| | 48 | For each channel, the relevant values for the channel status are: |
| | 49 | * CHANNEL_IDLE : channel not running |
| | 50 | * CHANNEL_SRC_DESC_ERROR : bus error accessing SRC CHBUF descriptor |
| | 51 | * CHANNEL_DST_DESC_ERROR : bus error accessing DST CHBUF descriptor |
| | 52 | * CHANNEL_SRC_DATA_ERROR : bus error accessing SRC CHBUF data |
| | 53 | * CHANNEL_DST_DATA_ERROR : bus error accessing DST CHBUF data |
| | 54 | * CHANNEL_BUSY : channel running |
| | 55 | |
| | 56 | There is one private IRQ line for each channel, that is only used for bus error signaling, and is activated when channel[k] enters |
| | 57 | n error state. The channel can be reset by writing a nul value in register CHBUF_RUN[k], focing channel[k] to IDLE state. |
| | 58 | // |
| | 59 | // In order to support multiple simultaneous transactions, the channel |
| | 60 | // index is transmited in the VCI TRDID field. |
