Changes between Version 4 and Version 5 of Component/Vci Chbuf Dma


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Timestamp:
Jan 13, 2015, 11:54:43 AM (10 years ago)
Author:
alain
Comment:

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  • Component/Vci Chbuf Dma

    v4 v5  
    1818The chbuf descriptor" base address must be a multiple of 64 bytes.
    1919
    20 This DMA controller implements two mode to scan the SRC and DST chbufs:
     20This DMA controller implements two modes to scan the SRC and DST chbufs:
    2121 * '''IN_ORDER_FIFO''': Both the source chained buffers and the destination chained buffers are accessed in strict order, as defined by the SRC and DST chbuf descriptors. The access is blocking until the expected buffer is available. If the buffer is not available, the delay before retry is defined by the software addressable register CHBUF_PERIOD. This register must be non zero to activate this mode.
    2222 * '''OUT_OF_ORDER''': The SRC and DST chbuf descriptors are scanned with a round robin priority. The first full SRC buffer found is read, and the first empty DST buffer found is written. This mode is activated when the CHBUF_PERIOD value is zero (default value).
    … …  
    2525In order to support multiple simultaneous transactions, the channel index is transmited in the VCI TRDID field.   
    2626
    27 The number of channels and the max burst size are constructor parameters:
     27The number of channels and the max burst length are constructor parameters:
    2828 * The number of channels (simultaneous transfers) cannot be larger than 8.
    29  * The burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. If the source and destinat aligned on a burst boundary, the DMA controler split the burst in two VCI transactions.
     29 * The max burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. If the source and/or destination buffers are not aligned on a burst boundary, the DMA controler split the burst in two VCI transactions.
    3030
    3131Each channel [k] has 10 memory-mapped 32 bits registers:
    32  * CHBUF_RUN[k]       (write-only) : channel activated when writing a non-zero value
     32 * CHBUF_RUN[k]       (write-only) : channel is activated when writing a non-zero value
    3333 * CHBUF_STATUS[k]    (read-only)  : channel status
    3434 * CHBUF_SRC_DESC[k]  (read/write) : SRC chbuf descriptor 32 LSB bits physical address