Changes between Version 5 and Version 6 of Component/Vci Chbuf Dma


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Timestamp:
Jul 15, 2015, 6:36:07 PM (9 years ago)
Author:
bellefin
Comment:

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  • Component/Vci Chbuf Dma

    v5 v6  
    1212The buffer length must be the same for the SRC chbuf and for the DST chbuf.
    1313
    14 A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''.
    15 Each buffer descriptor occupies 64 bytes, but only the first 8 bytes (64 bits) contain useful information:
    16  * The 48 LSB bits contain the buffer physical address
    17  * The MSB bit 63 defines the buffer state (empty if 0)
    18 The chbuf descriptor" base address must be a multiple of 64 bytes.
     14The state of each buffer must be defined in a variable called '''status'''. Each “status” occupies 64 bytes, but only the last bit is useful (1 if the buffer is full, 0 if it is empty). A buffer and its status physical addresses must be 64 bytes aligned and must have the same extension (identical bits[43:32]).
     15
     16A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''. Each buffer descriptor occupies 64 bits:
     17 * The 12 MSB bits contain the common extension of the buffer address and the buffer status address
     18 * The 26 following bits contain the bits [31:6] of the buffer address
     19 * The 26 LSB bits contain the bits [31:6] of the buffer status address
     20The "chbuf descriptor" base address must be a multiple of 64 bytes.
    1921
    2022This DMA controller implements two modes to scan the SRC and DST chbufs:
    2123 * '''IN_ORDER_FIFO''': Both the source chained buffers and the destination chained buffers are accessed in strict order, as defined by the SRC and DST chbuf descriptors. The access is blocking until the expected buffer is available. If the buffer is not available, the delay before retry is defined by the software addressable register CHBUF_PERIOD. This register must be non zero to activate this mode.
    22  * '''OUT_OF_ORDER''': The SRC and DST chbuf descriptors are scanned with a round robin priority. The first full SRC buffer found is read, and the first empty DST buffer found is written. This mode is activated when the CHBUF_PERIOD value is zero (default value).
     24 * '''OUT_OF_ORDER''': The SRC and DST chbuf descriptors and status are scanned with a round robin priority. The first full SRC buffer found is read, and the first empty DST buffer found is written. This mode is activated when the CHBUF_PERIOD value is zero (default value).
    2325
    2426This component supports both 32 bits and 64 bits VCI RDATA & WDATA fields, and supports VCI addresses up to 64 bits.
    25 In order to support multiple simultaneous transactions, the channel index is transmited in the VCI TRDID field.   
     27In order to support multiple simultaneous transactions, the channel index is transmitted in the VCI TRDID field.   
    2628
    27 The number of channels and the max burst length are constructor parameters:
    28  * The number of channels (simultaneous transfers) cannot be larger than 8.
    29  * The max burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width. If the source and/or destination buffers are not aligned on a burst boundary, the DMA controler split the burst in two VCI transactions.
     29The transfer between a SRC and a DST buffer is divided into several bursts, and more precisely into series of several pipelined bursts. In a series of pipelined bursts, all the read requests are sent successively and the responses are stored in a local fifo (one fifo per channel). Then the successive write commands are sent to the DST buffer.
     30
     31The number of channels, the max burst length and the number of stages in the pipeline are constructor parameters:
     32 * The number of channels (simultaneous transfers) cannot be larger than 8.
     33 * The max burst length (in bytes) must be a power of 2 no larger than 64, and is typically equal to the system cache line width.
     34 * The number of pipelined bursts cannot be larger than 4 (default parameter).
     35
     36The total storage capacity for transferred data is channels * pipelined_bursts * burst_max_length.
    3037
    3138Each channel [k] has 10 memory-mapped 32 bits registers:
    … …  
    4754
    4855For each channel, the relevant values for the channel status are the following:
    49  || Channel Status         || value ||                                           ||
    50  || CHANNEL_IDLE           || 0     || channel not running                       ||
    51  || CHANNEL_SRC_DESC_ERROR || 1     || bus error accessing SRC CHBUF descriptor  ||
    52  || CHANNEL_DST_DESC_ERROR || 2     || bus error accessing DST CHBUF descriptor  ||
    53  || CHANNEL_SRC_DATA_ERROR || 3     || bus error accessing SRC CHBUF data        ||
    54  || CHANNEL_DST_DATA_ERROR || 4     || bus error accessing DST CHBUF data        ||
    55  || CHANNEL_BUSY           || >4    || channel running                           ||
     56 || Channel Status           || value ||                                           ||
     57 || CHANNEL_IDLE             || 0     || channel not running                       ||
     58 || CHANNEL_SRC_DESC_ERROR   || 1     || bus error accessing SRC CHBUF descriptor  ||
     59 || CHANNEL_DST_DESC_ERROR   || 2     || bus error accessing DST CHBUF descriptor  ||
     60 || CHANNEL_SRC_STATUS_ERROR || 3     || bus error accessing SRC BUF status        ||
     61 || CHANNEL_DST_STATUS_ERROR || 4     || bus error accessing SRC BUF status        ||
     62 || CHANNEL_DATA_ERROR       || 5     || bus error accessing SRC or DST CHBUF data ||
     63 || CHANNEL_BUSY             || >5    || channel running                           ||
    5664
    57 There is one private IRQ line for each channel, that is only used for bus error signaling, and is activated when channel[k] enters
    58 an error state. The channel can be reset by writing a nul value in register CHBUF_RUN[k], focing channel[k] to IDLE state.
     65There is one private IRQ line for each channel, that is only used for bus error signalling, and is activated when channel[k] enters
     66an error state. The channel can be reset by writing a null value in register CHBUF_RUN[k], forcing channel[k] to IDLE state.
    5967
    6068This hardware component checks for segmentation violation, and can be used as a default target.
    … …  
    8189     sc_module_name name,   //  Component Name
    8290     const soclib::common::MappingTable &mt,   // MappingTable
    83      const soclib::common::IntTab &srcid,  // Initiator index
    84      const soclib::common::IntTab &tgtid,  // Target index
    85      const size_t burst_max_length,   //  Max number of bytes transfered in a burst
    86      const size_t channels );  // Number of channels
     91     const soclib::common::IntTab &srcid,   // Initiator index
     92     const soclib::common::IntTab &tgtid,   // Target index
     93     const uint32_t burst_max_length,   //  Max number of bytes transferred in a burst
     94     const uint32_t channels,   // Number of channels
     95     const uint32_t pipelined_bursts );  // Number of pipelined bursts
    8796}}}
    8897