Changes between Version 7 and Version 8 of Component/Vci Chbuf Dma


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Timestamp:
Nov 17, 2016, 3:10:46 PM (6 years ago)
Author:
alain
Comment:

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  • Component/Vci Chbuf Dma

    v7 v8  
    66
    77This component is a multi-channels DMA controller supporting chained buffers.
    8 It can be used to move a data stream (such as packets or video) from one set of chained buffers (SRC chbuf)
    9 to another set of chained buffers (DST chbuf), without involving software.
     8It can be used to move a data streams (such as network packets or video stream) from one set of chained buffers (SRC chbuf)
     9to another set of chained buffers (DST chbuf), with minimal software activity.
    1010
    1111All buffers must have the same length, and must be aligned on a 32 bits word boundary.
    1212The buffer length must be the same for the SRC chbuf and for the DST chbuf.
    1313
    14 The state of each buffer must be defined in a variable called '''status'''. Each “status” occupies 64 bytes, but only the last bit is useful (1 if the buffer is full, 0 if it is empty). A buffer and its status physical addresses must be 64 bytes aligned and must have the same extension (identical bits[43:32]).
     14The state of each buffer must be defined in a variable called '''status'''. Each “status” occupies 64 bytes, but only the LSB bit is useful (1 if the buffer is full, 0 if it is empty). A buffer and its status physical addresses must be 64 bytes aligned and must have the same extension (identical bits[43:32]).
    1515
    1616A '''chbuf descriptor''' is a circular array of '''buffer descriptors'''. Each buffer descriptor occupies 64 bits:
    … …  
    2424 * '''OUT_OF_ORDER''': The SRC and DST chbuf descriptors and status are scanned with a round robin priority. The first full SRC buffer found is read, and the first empty DST buffer found is written. This mode is activated when the CHBUF_PERIOD value is zero (default value).
    2525
     26A long as no error is reported, each channel FSM does not stop moving buffers, until it is reset by software.
     27
     28 There is one IRQ per channel, that is activated each time a buffer has been sucessfully moved from source chbuf to destination chbuf, or when
     29an address error has been reported. This IRQ is acknowledged by a read command to the channel status register.
     30
    2631This component supports both 32 bits and 64 bits VCI RDATA & WDATA fields, and supports VCI addresses up to 64 bits.
    2732In order to support multiple simultaneous transactions, the channel index is transmitted in the VCI TRDID field.   
    … …  
    3439 * The number of pipelined bursts cannot be larger than 4 (default parameter).
    3540
    36 The total storage capacity for transferred data is channels * pipelined_bursts * burst_max_length.
     41The total internal storage capacity for transferred data is (channels * pipelined_bursts * burst_max_length) bytes.
    3742
    3843Each channel [k] has 10 memory-mapped 32 bits registers:
    … …  
    4853 * CHBUF_DST_EXT[k]   (read/write) : DST chbuf descriptor 32 MSB bits physical address
    4954For extensibility issues, you should access the DMA using globally-defined offsets, and you should include file `soclib/chbuf_dma.h` in your software.
    50 In order to support various protection mechanisms, for each channel, the channel addressable registers takes 4K bytes in the address space.
     55In order to support virtualisation mechanisms, for each channel, the channel addressable registers takes 4K bytes in the address space.
    5156The following address bits are decoded .
    5257 * The 5 bits ADDRESS[4:0] define the target register.