Changes between Version 6 and Version 7 of Component/Vci Icu

Timestamp:

May 9, 2007, 4:28:06 PM (17 years ago)

Author:

Nicolas Pouillon

Comment:

--

Component/Vci Icu

@@ -7 +7 @@
 to 32 independent interrupt lines '''p_irq_in[i]''' to a single 
 '''p_irq''' interrupt line.
+
 The active state is high, and the output interrupt is the logical OR of all 
-input interrupts. 
-Each input interrupt can be individually masked
-using a memory mapped  32 bits register.
-This component can be addresse to return the index of the highest priority
+input interrupts.
+Each input interrupt can be individually masked through an internal register.
+
+This component can be addressed to return the index of the highest priority
 active interrupt '''p_irq_[i]'''. 
 The priority scheme is fixed : The lower indexes have the highest priority.
-The memory segment allocated to this component must be aligned
-on 8 bytes boundary.
-This hardware component cheks for segmentation violation, and can be used
+
+This hardware component checks for segmentation violation, and can be used
 as a default target.
 
-This component contains 2 memory mapped registers:
+= Memory region layout =
 
- * '''ICU_INDEX'''     : ADDRESS![2:0] = 0x0
-It is actually a 32 bits pseudo-register: A read request
-returns the index value of the highest priority active input interrupt.
-If there is no active interrupt, it returns the 32 value.
-This register is read-only.
+This component contains 5 memory mapped registers:
 
- * '''ICU_MASK''' : ADDRESS![2:0] = 0x4 
-Each bit i of this 32 bits register enables the corresponding 
-'''p_irq_in[i]''' input interrupt, when this bit is one.
-This register can be read or written.A write request of a zero gives resets this register.
-This register is write-only.
+ * `ICU_INT`: ADDRESS![4:0] = 0x0
+   Each bit in this register reflects the state of the corresponding interrupt line.
+   This is read-only.
+
+ * `ICU_MASK`: ADDRESS![4:0] = 0x4
+   Each bit in this register reflects the state of the enable for the corresponding interrupt line.
+   This is read-only.
+
+ * `ICU_MASK_SET`: ADDRESS![4:0] = 0x8
+   Each bit set in the written word will be set in the ICU MASK. (ICU_MASK = ICU_MASK | written_data).
+   This is write-only.
+
+ * `ICU_MASK_CLEAR`: ADDRESS![4:0] = 0xc
+   Each bit set in the written word will be reset in the ICU MASK. (ICU_MASK = ICU_MASK & ~written_data).
+   This is write-only.
+
+ * `ICU_IT_VECTOR`: ADDRESS![4:0] = 0x10
+   This register gives the number of the highest-priority active interrupt.
+   If no interrupt is active, (-1) is returned.
+   This is read-only.
+
+= Component usage =
+
+For extensibility issues, you should access your ICU using globally-defined offsets.
+
+You should include file source:trunk/soclib/include/soclib/icu.h from your software, it
+defines `ICU_INT`, `ICU_MASK`, `ICU_MASK_SET`, `ICU_MASK_CLEAR`, `ICU_IT_VECTOR`.
+
+Sample code:
+{{{
+#include "soclib/icu.h"
+
+static const volatile void* timer_address = 0xc0000000;
+
+static icu_test(const size_t icu_no)
+{
+    volatile int *icu = ((int*)icu_address) + timer_no*ICU_SPAN;
+
+    // Getting / setting interrupt mask
+    uint32_t current_interrupt_mask = icu[ICU_MASK];
+
+    // Enabling IRQ #5
+    icu[ICU_MASK_SET] = 0x20;
+    // Disabling IRQ #0
+    icu[ICU_MASK_CLEAR] = 0x1;
+
+    // When interrupt is raised, you may do:
+    int irq_to_serve = icu[ICU_IT_VECTOR];
+    // This should be equivalent to (see man 3 ffs)
+    int irq_to_serve = ffs(icu[ICU_IT_VECTOR] & icu[ICU_MASK]);
+}
+}}}
+
+(add -I/path/to/soclib/include to your compilation command-line)
 
 = !VciIcu CABA  Implementation =