Changes between Version 2 and Version 3 of Component/Vci Iopic

Timestamp:

Mar 8, 2014, 4:55:05 PM (10 years ago)

Author:

alain

Comment:

--

Component/Vci Iopic

@@ -5 +5 @@
 == 1) Functional Description ==
 
-This component is a multi-channels, programmable, Hardware Interrupt  to Software Interrupt translator. It can be used to translate a variable number of hardware interrupt lines (HWI) to the same number of write triggered interrupt (SWI) that can be handled by a !VciXicu component. It acts as a VCI initiator, to send a single flit VCI packet to the target interrupt controller, when a rising edge is detected on a given HWI input. It acts also as a memory mapped VCI target, as the addresses of the WTI associated to a given HWI must be configured by the software.
+This component is a multi-channels, programmable, Hardware Interrupt  to Software Interrupt translator. It can be used to translate a variable number of hardware interrupt lines (HWI) to the same number of write triggered interrupt (SWI) that can be handled by a !VciXicu component. It acts as a VCI initiator, to send a single flit VCI packet to the target !VciXicu interrupt controller, when a rising/falling edge is detected on a given HWI input. It acts also as a memory mapped VCI target, as the addresses of the WTI associated to a given HWI must be configured by the software.
 
 For each HWI channel, there is three 32 bits addressable registers:
@@ -15 +15 @@
 '''IOPIC_STATUS''' This READ-ONLY register register contains the HWI channel status. Only the two LSB bits are significant:
  * Bit 0 : HWI line current value.
- * Bit 1 : Error reported in a WTI transaction when tis bit is set.
+ * Bit 1 : ERROR reported in a WTI transaction when this bit is set.
 Any read access to the IOPIC status register reset the ERROR bit.