Changes between Version 5 and Version 6 of Component/Vci Iopic

Timestamp:

Sep 4, 2014, 4:16:46 PM (10 years ago)

Author:

alain

Comment:

--

Component/Vci Iopic

@@ -5 +5 @@
 == 1) Functional Description ==
 
-This component is a multi-channels, programmable, Hardware Interrupt  to Software Interrupt translator. It can be used to translate a variable number of hardware interrupt lines (HWI) to the same number of write triggered interrupt (SWI) that can be handled by a !VciXicu component. 
+This component is a multi-channels, programmable, Hardware Interrupt to Software Interrupt translator. It can be used to translate a number of hardware interrupt lines (HWI) to the same number of write triggered interrupt (SWI) that can be handled by a !VciXicu component. 
 
-It acts as a VCI initiator, to send a single flit VCI packet to the target !VciXicu interrupt controller, when a rising/falling edge is detected on a given HWI input. For each HWI channel, WTIs are periodically sent (each 5000 cycles) as long as the HWI input signal is high. 
+It acts as a VCI initiator, to send a single flit VCI packet to the target !VciXicu interrupt controller, when a rising/falling edge is detected on a given HWI input.
 
 It acts also as a memory mapped VCI target, as the addresses of the WTI associated to a given HWI must be configured by the software.
@@ -13 +13 @@
 It supports both 32 and 64 bits for the VCI data field width.
 
-For each HWI channel, there is three 32 bits addressable registers:
+For each HWI channel, there is four 32 bits addressable registers:
 
 '''IOPIC_ADDRESS''' This READ/WRITE register contains the 32 LSB bits of the physical WTI address associated to the HWI channel.
+The hardware RESET value is 0.
 
 '''IOPIC_EXTEND''' This READ/WRITE register contains the 32 MSB bits of the physical WTI address associated to the HWI channel.
+The hardware RESET value is 0.
+
+'''IOPIC_MASK''' This READ/WRITE register contains actually a boolean: the corresponding HWI will be transmitted as a WTI only if the register value is not 0. The hardware RESET value is 0. 
 
 '''IOPIC_STATUS''' This READ-ONLY register register contains the HWI channel status. Only the two LSB bits are significant:
@@ -23 +27 @@
  * Bit 1 : ERROR reported in a WTI transaction when this bit is set.
 Any read access to the IOPIC status register reset the ERROR bit.
+
+Besides these these 
 
 == 2) Component definition & usage