Changes between Version 14 and Version 15 of Component/Vci Master Nic


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Timestamp:
Jul 26, 2020, 12:27:53 PM (4 years ago)
Author:
alain
Comment:

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  • Component/Vci Master Nic

    v14 v15  
    1313To improve the throughput, this component supports up to 8 channels.
    1414These channels are indexed by an index derived from the (source) remote IP address and port for the received (RX) packets,
    15 and from the (destination) remote IP address and port for the sent (TX) packets.
     15and from the (destination) remote IP address and port for the sent (TX) packets:
     16{{{
     17            uint32_t key = ( ((addr     ) & 0xFF) +
     18                             ((addr > 8 ) & 0xFF) +
     19                             ((addr > 16) & 0xFF) +
     20                             ((addr > 24) & 0xFF) +
     21                             ((port     ) & 0xFF) +
     22                             ((port > 8 ) & 0xFF) ) % nb_channels;
     23}}}
    1624The actual number of channels is an hardware parameter.
    1725 
    … …  
    2230 * '''NIC_MODE_TAP''': The TX and RX packet streams are send and received to and from the physical network controller of the workstation running the simulation.
    2331
    24 The Ethernet packet length can have any value, in the range [42 to 1538] bytes.
     32The Ethernet packet length can have any value, in the range [42 to 2040] bytes.
    2533
    2634The minimal data transfer unit between software and the NIC is a 4K bytes '''container''',
    … …  
    2937
    3038The received packets (RX) and the sent packets (TX) are stored in
    31 two memory mapped software FIFOs, implemented as chained buffers.
    32 Each slot in these FIFOs is a 4 Kbytes container. The number of containers,
    33 defining the queue depth, is a software defined parameter.
     39two memory mapped software queues, called chained buffers, and defined by the ''nic_chbuf_s'' C structure. The number of containers, defining the queue depth, is a software defined parameter.
     40The physical addresses are used by the hardware NIC DMA engines.
     41{{{
     42struct nic_chbuf_s
     43{
     44    uint32_t   wid;                              /*! current container write index         */
     45    uint32_t   rid;                              /*! current container read index          */
     46    uint64_t   cont_pad[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers physical base addresses    */
     47    uint32_t * cont_ptr[SOCLIB_NIC_CHBUF_DEPTH]; /*! containers virtual base addresses     */
     48}
     49}}}
    3450
    35 The container is handled as an array of 32 bits word, with the following format:
    36 
    37 The first 45 words (180 bytes) define the fixed-format container header :
    38 ||   word0  ||  NB_WORDS || NB_PACKETS ||
    39 ||   word1  ||  PLEN[0]  || PLEN[1]    ||
    40 ||    ...   ||   ...     ||   ...      ||
    41 ||   word44 ||  PLEN[86] || PLEN[87]   ||
    42 
    43  * NB_PACKETS is the actual number of packets in the container.
    44  * NB_WORDS is the number of useful words in the container.
    45  * PLEN[i] is the number of bytes for packet[i].
    46 
    47 The packets are stored in the (1024 - 45) following words (3916 bytes),
    48 and the packets are word-aligned.
    49 
    50 For the DMA engines, a container has only two states (full or empty), defined
    51 by one single bit, called the container "status" (1 for full / 0 for empty).
    52 To access both the container status, and the data contained in the container, the DMA
    53 engines use two physical addresses, that are packed in a 64 bits ''container descriptor'':
    54  * desc[25:0]  contain bits[31:6] of the "status" physical address.
    55  * desc[51:26] contain bits[31:6] of the "buffer" physical address.
    56  * desc[63:52] contain bits[43:32] of the physical address, common for "status" and "buffer".
     51Each container contain one single Ethernet Packet.
     52The ''nic_cont_s'' C structure contains a 2040 bytes data buffer, the actual packet length, and
     53the container state : full (owned by the reader) / empty (owned by the writer).
     54Thist state variable is used as a SET/RESET flip-flop to synchronize the software server thread, and the hardware NIC DMA engine.
     55struct nic_cont_s
     56{{{
     57{
     58    uint8_t    buf[2040];                        /*! Ethernet packet (42 to 2040 bytes     */
     59    uint32_t   length;                           /*! actual packet length in bytes         */
     60    uint32_t   state;                            /*! zero == empty / non zero == full      */
     61}
     62}}}
    5763
    5864Inside the NIC controller, each channel implements a 2 slots chained buffer (two
    … …  
    7177 * the is_rx   bit   is sent in TRDID[2]   
    7278
    73 == 2) Addressable registers and buffers ==
     79== 2) Addressable registers ==
    7480
    7581The addressable registers can be split in two classes: ''global'' registers, and ''channel'' registers.