Changes between Version 18 and Version 19 of Component/Vci Master Nic


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Timestamp:
Jul 26, 2020, 2:13:48 PM (4 years ago)
Author:
alain
Comment:

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  • Component/Vci Master Nic

    v18 v19  
    2828containing one single Ethernet packet.
    2929
    30 The received packets (RX) and the sent packets (TX) are stored in two memory mapped software queues, called ''chained buffer'', and defined by the '''nic_chbuf_s'' C structure. Each slot in the queue is a ''container''. The number of containers, defining the queue depth, is a software defined parameter.
    31 The physical addresses are used by the hardware NIC DMA engines.
    32 The virtual addresses are used by the software NIC drivers.
     30The received packets (RX) and the sent packets (TX) are stored in two memory mapped software FIFO queues, called ''chained buffer'', and defined by the '''nic_chbuf_s''' C structure. Each slot in the queue is a ''container''. The number of containers, defining the FIFO depth, is a software defined parameter.
     31
    3332{{{
    3433struct nic_chbuf_s
    … …  
    4039}
    4140}}}
     41
     42The physical addresses are used by the hardware NIC DMA engines.
     43The virtual addresses are used by the software NIC drivers.
    4244
    4345The '''nic_cont_s''' C structure contains a 2040 bytes data buffer, the actual ethernet packet length (in bytes), and the container state : full (owned by the reader) / empty (owned by the writer).
    … …  
    163165 * '''p_rx_irq[k]''' : As many RX IRQ ports as the number of channels
    164166 * '''p_tx_irq[k]''' : As many TX IRQ ports as the number of channels
    165