Changes between Version 21 and Version 22 of Component/Vci Master Nic

Timestamp:

Jul 30, 2020, 3:21:40 PM (4 years ago)

Author:

alain

Comment:

--

Component/Vci Master Nic

@@ -65 +65 @@
 chained buffer implementing the TX queue in memory, to the internal TX 2 slots chained buffer.
 
+=== 1.3 pipe-lined transfers ===
+
 To improve the throughput for one specific channel, the DMA engines use ''pipelined bursts'': The burst length 
 cannot be larger than 64 bytes, but each channel send 4 pipelined VCI transactions to mask the round-trip latency. 
@@ -73 +75 @@
  * the is_rx   bit   is sent in TRDID[2]    
 
-=== 1.3 GMII physical interface ===
+=== 1.4 hard/soft synchronisation ===
+
+Regarding the TX paquets, the TX_DMA[k] engines (one TX DMA per channel) implement a polling policy on the TX queue, with a delay (defined by the TX_DMA_PERIOD hardware parameter) between retry if the TX queue is empty. It signals the TX server thread with an IRQ when the TX queue changes from the full state, to non-full.
+
+Regarding the RX paquets, the RX_DMA[k] engines (one RX DMA per channel) implement a polling policy on the RX queue, with a delay (defined by the RX_DMA_PERIOD hardware parameter) between retry if the RX queue is full. It signals the RX server thread with an IRQ when the TR queue changes from the empty state, to non-empty.
+
+=== 1.5 GMII physical interface modeling ===
 
 The SystemC simulation model supports three modes of operation, defined by a constructor parameter: