Changes between Version 22 and Version 23 of Component/Vci Master Nic

Timestamp:

Jul 30, 2020, 3:26:56 PM (4 years ago)

Author:

alain

Comment:

--

Component/Vci Master Nic

@@ -30 +30 @@
 === 1.1 Software queues ===
 
-The received packets (RX) and the sent packets (TX) are stored in two memory mapped software FIFO queues, called ''chained buffer'', and defined by the '''nic_chbuf_s''' C structure. Each slot in the queue is a ''container''. The number of containers, defining the FIFO depth, is a software defined parameter.
+The received packets (RX) and the sent packets (TX) are stored in two memory mapped queues, handled as software FIFOs. They are and called ''chained buffer'', and defined by the '''nic_chbuf_s''' C structure. Each slot in the queue is a ''container''. Each container can contain one single UDP packet or TCP segment. The number of containers, defining the FIFO depth, is a software defined parameter.
 
 {{{
@@ -48 +48 @@
 
 The '''nic_cont_s''' C structure contains a 2040 bytes data buffer, the actual ethernet packet length (in bytes), and the container state : full (owned by the reader) / empty (owned by the writer).
-Thist state variable is used as a SET/RESET flip-flop to synchronize the software server thread, and the hardware NIC DMA engine. 
+Thist state variable is used as a SET/RESET flip-flop, by the software server thread, and the hardware NIC DMA engine. 
 {{{
 struct nic_cont_s