Changes between Version 6 and Version 7 of Component/Vci Master Nic


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Timestamp:
Apr 1, 2020, 7:43:25 PM (5 years ago)
Author:
alain
Comment:

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  • Component/Vci Master Nic

    v6 v7  
    1111is larger or equal to the GMII clock frequency (ie 125 MHz).
    1212
    13 To improve the throughput, this component supports up to 8 channels,
    14 indexed by the (remote) source IP address for the received (RX) packets,
    15 and indexed by the (remote) destination IP address for the sent (TX) packets.
     13To improve the throughput, this component supports up to 8 channels.
     14These channels are indexed by an index derived from the (source) remote IP address and port for the received (RX) packets,
     15and from the (destination) remote IP address and port for the sent (TX) packets.
    1616The actual number of channels is an hardware parameter.
    1717 
    … …  
    2222 * '''NIC_MODE_TAP''': The TX and RX packet streams are send and received to and from the physical network controller of the workstation running the simulation.
    2323
    24 The packet length can have any value, from 60 to 1514 bytes.
     24The packet length can have any value, in the range [54 to 1514] bytes.
    2525
    2626The minimal data transfer unit between software and the NIC is a 4K bytes '''container''',
    … …  
    4949
    5050For the DMA engines, a container has only two states (full or empty), defined
    51 by a single bit, called the container "status".
     51by one single bit, called the container "status" (1 for full / 0 for empty).
    5252To access both the container status, and the data contained in the container, the DMA
    5353engines use two physical addresses, that are packed in a 64 bits ''container descriptor'':
    54  * desc[25:0]  contain bits[31:6] of the "full" status physical address.
     54 * desc[25:0]  contain bits[31:6] of the "status" physical address.
    5555 * desc[51:26] contain bits[31:6] of the "buffer" physical address.
    56  * desc[63:52] contain the common 12 physical address extension bits.
     56 * desc[63:52] contain bits[43:32] of the physical address, common for "status" and "buffer".
    5757
    5858Inside the NIC controller, each channel implements a 2 slots chained buffer (two
    … …  
    6060For each channel,  the build-in RX_DMA engine moves the RX containers from
    6161the internal 2 slots chained buffer to the external chained buffer implementing
    62 the RX queue in memory.
    63 Another build-in TX-DMA engine moves the TX containers from the external
    64 chained buffer implementing the TX queue in memory, to the internal TX 2 slots
    65 chained buffer.
     62the RX queue in memory. Another build-in TX-DMA engine moves the TX containers from the external
     63chained buffer implementing the TX queue in memory, to the internal TX 2 slots chained buffer.
    6664
    6765To improve the throughput for one specific channel, the DMA engines use ''pipelined bursts'': The burst length cannot be larger than 64 bytes, but each channel send 4 pipelined VCI transactions to mask the round-trip latency. Therefore, thi NIC controller can control up to 32 parallel VCI transactions (4 channels * 4 bursts * 2 directions).