Changes between Version 8 and Version 9 of Component/Vci Master Nic


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Timestamp:
Apr 2, 2020, 9:02:46 PM (5 years ago)
Author:
alain
Comment:

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  • Component/Vci Master Nic

    v8 v9  
    1212
    1313To improve the throughput, this component supports up to 8 channels.
    14 These channels are indexed by an index derived from the (source) remote IP address and port  for the received (RX) packets,
     14These channels are indexed by an index derived from the (source) remote IP address and port for the received (RX) packets,
    1515and from the (destination) remote IP address and port for the sent (TX) packets.
    1616The actual number of channels is an hardware parameter.
    … …  
    2222 * '''NIC_MODE_TAP''': The TX and RX packet streams are send and received to and from the physical network controller of the workstation running the simulation.
    2323
    24 The packet length can have any value, in the range [54 to 1514] bytes.
     24The Ethernet packet length can have any value, in the range [44 to 1514] bytes.
    2525
    2626The minimal data transfer unit between software and the NIC is a 4K bytes '''container''',
    2727containing an integer number of variable size packets.
    28 The max number of packets in a container is 66 packets.
     28The max number of packets in a container is 88 packets.
    2929
    3030The received packets (RX) and the sent packets (TX) are stored in
    … …  
    3333defining the queue depth, is a software defined parameter.
    3434
    35 The container format is defined below:
     35The container is handled as an array of 32 bits word, with the following format:
    3636
    37 The first 34 words define the fixed-format container header :
     37The first 45 words (180 bytes) define the fixed-format container header :
    3838||   word0  ||  NB_WORDS || NB_PACKETS ||
    3939||   word1  ||  PLEN[0]  || PLEN[1]    ||
    4040||    ...   ||   ...     ||   ...      ||
    41 ||   word33 ||  PLEN[64] || PLEN[65]   ||
     41||   word44 ||  PLEN[86] || PLEN[87]   ||
    4242
    4343 * NB_PACKETS is the actual number of packets in the container.
    … …  
    4545 * PLEN[i] is the number of bytes for packet[i].
    4646
    47 The packets are stored in the (1024 - 34) following words,
    48 The max number of packets in a container is 66 packets, and the packets are word-aligned.
     47The packets are stored in the (1024 - 45) following words (3916 bytes),
     48and the packets are word-aligned.
    4949
    5050For the DMA engines, a container has only two states (full or empty), defined
    … …  
    6363chained buffer implementing the TX queue in memory, to the internal TX 2 slots chained buffer.
    6464
    65 To improve the throughput for one specific channel, the DMA engines use ''pipelined bursts'': The burst length cannot be larger than 64 bytes, but each channel send 4 pipelined VCI transactions to mask the round-trip latency. Therefore, thi NIC controller can control up to 32 parallel VCI transactions (4 channels * 4 bursts * 2 directions).
     65To improve the throughput for one specific channel, the DMA engines use ''pipelined bursts'': The burst length
     66cannot be larger than 64 bytes, but each channel send 4 pipelined VCI transactions to mask the round-trip latency.
     67Therefore, this NIC controller can control up to 64 parallel VCI transactions (8 channels * 4 bursts * 2 directions).
    6668The CMD/RSP matching uses both the VCI TRDID and PKTID fields:
    67  * the channel index is sent in TRDID[3:2]
     69 * the channel index is sent in SRCID
    6870 * the burst   index is sent in TRDID[1:0]
    69  * the is_rx   bit   is sent in SRCID    
     71 * the is_rx   bit   is sent in TRDID[2]   
    7072
    7173== 2) Addressable registers and buffers ==