Changes between Version 1 and Version 2 of Component/Vci Multi Dma


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Timestamp:
Apr 13, 2011, 2:23:53 PM (14 years ago)
Author:
alain
Comment:

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  • Component/Vci Multi Dma

    v1 v2  
    1111 * It is acting as an initiator to do the transfer.
    1212
    13 This hardware component supports up to 16 simultaneous DMA transfers,
    14 corresponding to 16 independant DMA channels.
     13The !VCIMultiDma component supports up to 16 simultaneous DMA transfers,
     14corresponding to 16 independant DMA channels. As there is only one VCI port, the general arbitration policy between the active channels is round-robin.
    1515
    16 As there is only one VCI port, the general arbitration policy between the
    17 active channels is round-robin.
     16The number of channels and the max burst length are constructor parameters.
     17The burst length parameter must be multiple of 4 bytes.
    1818
    19 Each channet has its own set of memory mapped registers, and for each
     19This component makes the assumption that the VCI RDATA & WDATA fiels have 32 bits.
     20The source buffer base address, the destination buffer base address and the buffer length
     21mus be multiple of 4 bytes. The buffer length is not constrained to be a multiple of
     22the burst length.
     23
     24Each channel has its own set of memory mapped registers, and for each
    2025channel a specific IRQ can be is optionally asserted when transfer is completed.
    2126
    22 This hardware component checks for segmentation violation, and can be used
    23 as a default target.
     27Each channel k has 5 memory-mapped registers :
    2428
    25 This component has 5 memory-mapped registers :
    26 
    27  * '''DMA_SRC''' (Read / Write)
     29 * '''DMA_SRC[k]''' (Read / Write)
    2830It defines the physical address of the source buffer.
    2931
    30  * '''DMA_DST''' (Read / Write)
     32 * '''DMA_DST[k]''' (Read / Write)
    3133It defines the physical address of the destination buffer.
    3234
    33  * '''DMA_LEN''' (Read / Write)
     35 * '''DMA_LEN[k]''' (Read / Write)
    3436It defines the length of transfer, in bytes. This register must be written after writing into
    3537registers DMA_SRC & DMA_DST, as the writing into the DMA_LEN register starts the transfer.
    … …  
    3739This register can be used to test the DMA coprocessor status.
    3840
    39  * '''DMA_RESET''' (Write-only)
     41 * '''DMA_RESET[k]''' (Write-only)
    4042Writing any value into this pseudo-register makes a clean re-initialisation of the DMA coprocessor:
    4143The on-going VCI transaction is completed before the coprocessor returns the IDLE state.
    4244This write access must be used by the software ISR to aknowledge the DMA IRQ.
    4345
    44  * '''DMA_IRQ_DISABLED''' (Read / Write)
     46 * '''DMA_IRQ_DISABLED[k]''' (Read / Write)
    4547A non zero value disables the IRQ line. The RESET value is zero.
    4648
    47 For extensibility issues, you should access the DMA using globally-defined offsets.
     49The aligned segment size associated to this VCI target is 1 Kbytes, as only 10 address bits are decoded : the 6 MSB bits define the target register, and the next 4 bits define the channel index.
    4850
    49 You should include file `soclib/dma.h` from your software, it
     51For extensibility issues, you should access the DMA using globally-defined offsets, and
     52you should include file `soclib/dma.h` in your software, it
    5053defines `DMA_SRC`, `DMA_DST`, `DMA_LEN`, `DMA_RESET`, `DMA_IRQ_DISABLED`.
    5154
    52 Sample code:
    53 {{{
    54 #include "soclib/dma.h"
    55 
    56 static const volatile void* dma = 0xc0000000;
    57 
    58 void * memcpy(void *dst, const void *src, const size_t len)
    59 {
    60     soclib_io_set( dma, DMA_DST, dst );
    61     soclib_io_set( dma, DMA_SRC, src );
    62     soclib_io_set( dma, DMA_LEN, len );
    63     while( soclib_io_get( dma, DMA_LEN ) )
    64         ;
    65     return dst;
    66 }
    67 
    68 }}}
    69 
    70 (add -I/path/to/soclib/include to your compilation command-line)
     55This hardware component checks for segmentation violation, and can be used
     56as a default target.
    7157
    7258== 2) Component definition & usage ==
    7359
    74 source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_dma/caba/metadata/vci_dma.sd
     60source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_multi_dma/caba/metadata/vci_multi_dma.sd
    7561
    7662See [wiki:SoclibCc/VciParameters SoclibCc/VciParameters]
    7763{{{
    78 Uses( 'vci_dma' )
     64Uses( 'vci_multi_dma' )
    7965}}}
    8066
    … …  
    8369=== CABA sources ===
    8470 
    85  * interface : source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_dma/caba/source/include/vci_dma.h
    86  * implementation : source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_dma/caba/source/src/vci_dma.cpp
     71 * interface : source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_multi_dma/caba/source/include/vci_multi_dma.h
     72 * implementation : source:trunk/soclib/soclib/module/infrastructure_component/dma_infrastructure/vci_multi_dma/caba/source/src/vci_multi_dma.cpp
    8773
    8874=== CABA Constructor parameters ===
    … …  
    9379     const soclib::common::IntTab &srcid,  // Initiator index
    9480     const soclib::common::IntTab &tgtid,  // Target index
    95      const size_t burst_size );   //  Number of bytes transfered in a burst
     81     const size_t burst_size,   //  Max number of bytes transfered in a burst
     82     const size_t channels );  // Number of channels
    9683}}}
    9784
    9885===  CABA Ports ===
    9986
    100  * sc_in<bool> '''p_resetn''' : Global system reset
    101  * sc_in<bool> '''p_clk''' : Global system clock
    102  * soclib::caba::!VciTarget<vci_param> '''p_vci_target''' : The VCI target port
    103  * soclib::caba::!VciInitiator<vci_param> '''p_vci_initiator''' : The VCI initiator port
    104  * sc_out<bool> '''p_irq''' : Interrupt port
     87 * '''p_resetn''' : Global system reset
     88 * '''p_clk''' : Global system clock
     89 * '''p_vci_target''' : The VCI target port
     90 * '''p_vci_initiator''' : The VCI initiator port
     91 * '''p_irq[k]''' : As many output IRQ ports as the number of channels
    10592
    10693== 4) TLM-DT implementation ==