Changes between Version 5 and Version 6 of Component/Vci Multi Dma

Timestamp:

Dec 10, 2011, 5:23:52 PM (13 years ago)

Author:

alain

Comment:

--

Component/Vci Multi Dma

@@ -23 +23 @@
 
 Each channel has its own set of memory mapped registers, and for each
-channel a specific IRQ can be is optionally asserted when transfer is completed.
+channel a specific IRQ can be optionally asserted when transfer is completed.
 
 Each channel k has 5 memory-mapped registers :
@@ -34 +34 @@
 
  * '''DMA_LEN[k]''' (Read / Write)
-It defines the length of transfer, in bytes. This register must be written after writing into 
-registers DMA_SRC & DMA_DST, as the writing into the DMA_LEN register starts the transfer. 
+Writing in this register defines the length of transfer (in bytes), and starts the transfer. 
 This register gets back to 0 when transfer is finished.
 This register can be used to test the DMA coprocessor status.