Changes between Initial Version and Version 1 of Component/Vci Multi Nic


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Timestamp:
Mar 16, 2015, 8:14:23 PM (10 years ago)
Author:
alain
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  • Component/Vci Multi Nic

    v1 v1  
     1[wiki:Component SocLib Components General Index]
     2
     3= !VciMultiNic =
     4
     5== 1) Functional Description ==
     6
     7The !VciMultiNic component, is a multi-channels, GMII compliant, network controller
     8for Gigabit Ethernet network.
     9
     10It can support a throughput of 1 Gigabit/s, as long as the system clock frequency
     11is larger or equal to the GMII clock frequency (ie 125 MHz).
     12
     13Each channel defines a different destination MAC address, and each channel uses private RX and TX buffers.
     14The number of channels is a constructor parameter, and cannot be larger than 8.
     15
     16On the VCI side, this component makes the assumption that the VCI RDATA & WDATA fields have 32 bits.
     17
     18Regarding the GMII physical interface, this simulation model supports three modes
     19of operation, defined by a constructor parameter:
     20 * '''NIC_MODE_FILE''': Both the RX packets stream an the TX packets stream are read/written from/to dedicated files "nic_rx_file.txt" and "nic_tx_dile.txt", stored in the same directory as the top.cpp file.
     21 * '''NIC_MODE_SYNTHESIS''': The TX packet stream is still written to the "nic_tx_file.txt" file, but the RX packet stream is synthesised. The packet length (between 64 and 1538 bytes) and the source MAC address (8 possible values) are pseudo-random numbers.
     22 * '''NIC_MODE_TAP''': The TX and RX packet streams are send and received to and from the physical network controller of the workstation running the simulation.
     23
     24It is a VCI target with no DMA capability : All data transfers must be performed by software, or by the external !VciChbufDma component.
     25
     26The data transfer unit between software and the NIC is a fixed-size '''container''', containing an integer number of packets. A container is a 4 Kbytes buffer (1024 words of 32 bits).
     27
     28The first 34 words define the fixed-format container header :
     29||   word0  ||  NB_WORDS || NB_PACKETS ||
     30||   word1  ||  PLEN[0]  || PLEN[1]    ||
     31||    ...   ||   ...     ||   ...      ||
     32||   word33 ||  PLEN[64] || PLEN[65]   ||
     33
     34 * NB_PACKETS is the actual number of packets in the container.
     35 * NB_WORDS is the number of useful words in the container.
     36 * PLEN[i] is the number of bytes for packet[i].
     37
     38The packets are stored in the (1024 - 34) following words,
     39The max number of packets in a container is 66 packets, and the packets are word-aligned.
     40
     41Each channel contains two RX containers and two TX containers. The two RX containers are organized as a '''RX_CHBUF''', and the two TX containers are organized as a '''TX_CHBUF'''.
     42
     43A ''CHBUF'' is a set of M chained buffers, plus a ''CHBUF_descriptor''. A ''CHBUF_descriptor'' is an array of M ''buffer_descriptors''.
     44A ''buffer descriptor'' contains the buffer base address PADDR (in the physical address space), and the buffer status STS (boolean : true => full / false => empty).
     45
     46In order to simplify the L2/L3 cache coherence, each buffer descriptor is actually implemented as a 64 bytes record, even if only the first 8 bytes  contain useful information( PADDR : bits[47:0] ) / STS : bit 63 ). 
     47
     48This ''CHBUF'' organization allows the TX or RX buffers to be accessed by the  !VciChbufDma engine.
     49
     50
     51== 2) Addressable registers and buffers ==
     52
     53In a virtualized environment each channel segment will be mapped in the address space of a different virtual machine.
     54Each channel takes a segment of 32 Kbytes in the address space, to simplify the address decoding, but only 20K bytes are used.
     55
     56 * The first 4 Kbytes contain the RX_0 container data
     57 * The next  4 Kbytes contain the RX_1 container data
     58 * The next  4 Kbytes contain the TX_0 container data
     59 * The next  4 Kbytes contain the TX_1 container data
     60 * The next  4 Kbytes contain the channel addressable registers:
     61
     62|| NIC_RX_DESC_LO_0  || RX_0 descriptor low word  || read/write ||
     63|| NIC_RX_DESC_HI_0  || RX_0 descriptor high word || read/write ||
     64|| NIC_RX_DESC_LO_1  || RX_1 descriptor low word  || read/write ||
     65|| NIC_RX_DESC_HI_1  || RX_1 descriptor high word || read/write ||
     66|| NIC_TX_DESC_LO_0  || TX_0 descriptor low word  || read/write ||
     67|| NIC_TX_DESC_HI_0  || TX_0 descriptor high word || read/write ||
     68|| NIC_TX_DESC_LO_1  || TX_1 descriptor low word  || read/write ||
     69|| NIC_TX_DESC_HI_1  || TX_1 descriptor high word || read/write ||
     70|| NIC_MAC_4         || MAC address 32 LSB bits   || read_only  ||
     71|| NIC_MAC_2         || MAC address 16 MSB bits   || read_only  ||
     72|| NIC_RX_RUN        || RX channel activated      || write_only ||
     73|| NIC_TX_RUN        || TX channel  activated     || write_only ||
     74
     75
     76On top of the channels segments is the hypervisor segment, taking 4 Kbytes,
     77and containing the global configuration registers: (all read/write).
     78In a virtualized environment, the corresponding page should not be mapped
     79in the virtual machines address spaces, as it should not accessed by the virtual machines.
     80|| Register name         || function                                       || Reset value  ||
     81|| NIC_G_VIS             || bitfield / bit N = 0 -> channel N is disabled  || all inactive ||
     82|| NIC_G_ON              || NIC active if non zero (inactive at reset)     || inactive     ||
     83|| NIC_G_BC_ENABLE       || boolean / broadcast enabled if true            || disabled     ||
     84|| NIC_G_TDM_ENABLE      || boolean / enable TDM dor TX if true            || disabled     ||
     85|| NIC_G_TDM_PERIOD      || value of TDM time slot                         ||              ||
     86|| NIC_G_PYPASS_ENABLE   || boolean / enable bypass for TX if true         || enabled      ||
     87|| NIC_G_MAC_4[8]        || default MAC address 32 LSB bits for channel[i] ||              ||
     88|| NIC_G_MAC_2[8]        || default MAC address 16 LSB bits for channel[i] ||              ||
     89
     90The Hypervisor segment contains also various event counters for statistics (read/write)
     91
     92|| NIC_G_NPKT_RX_G2S_RECEIVED       || number of packets received on GMII RX port      ||
     93|| NIC_G_NPKT_RX_G2S_DISCARDED      || number of RX packets discarded by RX_G2S FSM    ||
     94||                                  ||                                                 ||
     95|| NIC_G_NPKT_RX_DES_SUCCESS        || number of RX packets transmited by RX_DES FSM   ||
     96|| NIC_G_NPKT_RX_DES_TOO_SMALL      || number of discarded too small RX packets        ||
     97|| NIC_G_NPKT_RX_DES_TOO_BIG        || number of discarded too big RX packets          ||
     98|| NIC_G_NPKT_RX_DES_MFIFO_FULL     || number of discarded RX packets for fifo full    ||
     99|| NIC_G_NPKT_RX_DES_CRC_FAIL       || number of discarded RX packets for checksum     ||
     100||                                  ||                                                 ||
     101|| NIC_G_NPKT_RX_DISPATCH_RECEIVED  || number of packets received by RX_DISPATCH FSM   ||
     102|| NIC_G_NPKT_RX_DISPATCH_BROADCAST || number of broadcast RX packets received         ||
     103|| NIC_G_NPKT_RX_DISPATCH_DST_FAIL  || number of discarded RX packets for DST MAC      ||
     104|| NIC_G_NPKT_RX_DISPATCH_CH_FULL   || number of discarded RX packets for channel full ||
     105||                                  ||                                                 ||
     106|| NIC_G_NPKT_TX_DISPATCH_RECEIVED  || number of packets received by TX_DISPATCH FSM   ||
     107|| NIC_G_NPKT_TX_DISPATCH_TOO_SMALL || number of discarded too small TX packets        ||
     108|| NIC_G_NPKT_TX_DISPATCH_TOO_BIG   || number of discarded too big TX packets          ||
     109|| NIC_G_NPKT_TX_DISPATCH_SRC_FAIL  || number of discarded TX packets because SRC MAC  ||
     110|| NIC_G_NPKT_TX_DISPATCH_BROADCAST || number of broadcast TX packets received         ||
     111|| NIC_G_NPKT_TX_DISPATCH_BYPASS    || number of bypassed TX->RX packets               ||
     112|| NIC_G_NPKT_TX_DISPATCH_TRANSMIT  || number of transmit TX packets                   ||
     113
     114For extensibility issues, you should access all these registers using the globally-defined offsets in file
     115 source:trunk/soclib/soclib/module/connectivity_component/vci_multi_nic/include/soclib/multi_nic.h
     116
     117This hardware component checks for segmentation violation, and can be used as a default target.
     118
     119== 3) Component definition & usage ==
     120
     121source:trunk/soclib/soclib/module/connectivity_component/vci_multi_nic/caba/metadata/vci_multi_nic.sd
     122
     123{{{
     124Uses( 'vci_multi_nic' )
     125}}}
     126
     127== 4) CABA  Implementation ==
     128
     129=== CABA sources ===
     130 
     131 * interface : source:trunk/soclib/soclib/module/connectivity_component/vci_multi_nic/caba/source/include/vci_multi_nic.h
     132 * implementation : source:trunk/soclib/soclib/module/connectivity_component/vci_multi_nic/caba/source/src/vci_multi_nic.cpp
     133
     134=== CABA Constructor parameters ===
     135{{{
     136VciMultiNic(
     137     sc_module_name name,   //  Component Name
     138     const soclib::common::IntTab &tgtid,  // Target index
     139     const soclib::common::MappingTable &mt,   // MappingTable
     140     const size_t channels,   // Number of channels
     141     const uint32_t mac4,   //  MAC address 32 LSB bits
     142     const uint32_t mac2,   //  MAC address 16 MSB bits
     143     const int mode );    // GMII physical interface modeling
     144
     145}}}
     146
     147===  CABA Ports ===
     148
     149 * '''p_resetn''' : Global system reset
     150 * '''p_clk''' : Global system clock
     151 * '''p_vci''' : The VCI target port
     152 * '''p_rx_irq[k]''' : As many RX output IRQ ports as the number of channels
     153 * '''p_tx_irq[k]''' : As many TX output IRQ ports as the number of channels
     154
     155== 4) TLM-DT implementation ==
     156
     157The TLM-DT implementation is not available yet.