Changes between Version 2 and Version 3 of Component/Vci Multi Nic


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Timestamp:
Jul 15, 2015, 6:44:57 PM (10 years ago)
Author:
bellefin
Comment:

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  • Component/Vci Multi Nic

    v2 v3  
    4141Each channel contains two RX containers and two TX containers. The two RX containers are organized as a '''RX_CHBUF''', and the two TX containers are organized as a '''TX_CHBUF'''.
    4242
    43 A ''CHBUF'' is a set of M chained buffers, plus a ''CHBUF_descriptor''. A ''CHBUF_descriptor'' is an array of M ''buffer_descriptors''.
    44 A ''buffer descriptor'' contains the buffer base address PADDR (in the physical address space), and the buffer status STS (boolean : true => full / false => empty).
     43A ''CHBUF'' is a set of M chained buffers, M status variables, plus a ''CHBUF_descriptor''. A ''CHBUF_descriptor'' is an array of M ''buffer_descriptors''. The status LSB is a boolean which is true when the buffer is full and false when it is empty. A ''buffer_descriptor'' contains the buffer base address and the buffer status base address PADDR (in the physical address space). Both the addresses are 64 bytes aligned and they have the same address extension (bits[43:32]).
    4544
    46 In order to simplify the L2/L3 cache coherence, each buffer descriptor is actually implemented as a 64 bytes record, even if only the first 8 bytes  contain useful information( PADDR : bits[47:0] ) / STS : bit 63 ).
     45In order to simplify the L2/L3 cache coherence, each status variable is implemented as a 64 bytes record, even if only the last bit contain useful information. A ''buffer_descriptor'' occupies 64 bits: the 12 MSB bits contain the common extension of the buffer address and the buffer status address, the 26 following bits contain the bits[31:6] of the buffer address and the 26 LSB bits contain the bits[31:6] of the buffer status address.
    4746
    4847This ''CHBUF'' organization allows the TX or RX buffers to be accessed by the  !VciChbufDma engine.
    … …  
    6059 * The next  4 Kbytes contain the channel addressable registers:
    6160
    62 || NIC_RX_DESC_LO_0  || RX_0 descriptor low word  || read/write ||
    63 || NIC_RX_DESC_HI_0  || RX_0 descriptor high word || read/write ||
    64 || NIC_RX_DESC_LO_1  || RX_1 descriptor low word  || read/write ||
    65 || NIC_RX_DESC_HI_1  || RX_1 descriptor high word || read/write ||
    66 || NIC_TX_DESC_LO_0  || TX_0 descriptor low word  || read/write ||
    67 || NIC_TX_DESC_HI_0  || TX_0 descriptor high word || read/write ||
    68 || NIC_TX_DESC_LO_1  || TX_1 descriptor low word  || read/write ||
    69 || NIC_TX_DESC_HI_1  || TX_1 descriptor high word || read/write ||
    70 || NIC_MAC_4         || MAC address 32 LSB bits   || read_only  ||
    71 || NIC_MAC_2         || MAC address 16 MSB bits   || read_only  ||
    72 || NIC_RX_RUN        || RX channel activated      || write_only ||
    73 || NIC_TX_RUN        || TX channel  activated     || write_only ||
     61|| NIC_RX_STS_0      || RX_0 status (full or empty) || read/write ||
     62|| NIC_RX_STS_1      || RX_1 status (full or empty) || read/write ||
     63|| NIC_TX_STS_0      || TX_0 status (full or empty) || read/write ||
     64|| NIC_TX_STS_1      || TX_1 status (full or empty) || read/write ||
     65|| NIC_RX_DESC_LO_0  || RX_0 descriptor low word    || read/write ||
     66|| NIC_RX_DESC_HI_0  || RX_0 descriptor high word   || read/write ||
     67|| NIC_RX_DESC_LO_1  || RX_1 descriptor low word    || read/write ||
     68|| NIC_RX_DESC_HI_1  || RX_1 descriptor high word   || read/write ||
     69|| NIC_TX_DESC_LO_0  || TX_0 descriptor low word    || read/write ||
     70|| NIC_TX_DESC_HI_0  || TX_0 descriptor high word   || read/write ||
     71|| NIC_TX_DESC_LO_1  || TX_1 descriptor low word    || read/write ||
     72|| NIC_TX_DESC_HI_1  || TX_1 descriptor high word   || read/write ||
     73|| NIC_MAC_4         || MAC address 32 LSB bits     || read_only  ||
     74|| NIC_MAC_2         || MAC address 16 MSB bits     || read_only  ||
     75|| NIC_RX_RUN        || RX channel activated        || write_only ||
     76|| NIC_TX_RUN        || TX channel  activated       || write_only ||
    7477
    7578
    … …  
    141144     const uint32_t mac4,   //  MAC address 32 LSB bits
    142145     const uint32_t mac2,   //  MAC address 16 MSB bits
    143      const int mode );    // GMII physical interface modeling
     146     const int mode,   // GMII physical interface modeling
     147     const uint32_t inter_frame_gap);   // delay between two packets
    144148
    145149}}}